Difference between pages "KA11 CPU" and "PDP-11 Memory Management"

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m (→‎External links: +Details of Design, KA11)
 
m (→‎Further reading: +Extended Memory for the LSI-11)
 
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[[Image:KA11FrontPanel.jpg|right|thumb|300px|KA11 [[front panel]]]]
+
[[PDP-11]]s which provide [[memory management]] use a standard '''PDP-11 Memory Management''' [[architecture]]. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '[[segment]]s' (the terminology used in the first version of the documentation; it was later changed to 'pages', for unknown reasons, but this is incorrrect - the functionality provided is that of segmentation, not [[virtual memory|paging]]).
  
−
The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP-11 CPU which was not [[microcode]]d (since the cheap [[read-only memory|ROMs]] which make micro-programming cost-effective in smaller machines were not available at the time it was designed).
+
Each segment of a virtual address space can be individually assigned to any location in physical [[main memory]]. Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow down (from higher addresses to lower).
  
−
The KA11 was implemented as a set of [[DEC card form factor|extended length]] [[FLIP CHIP]]s, containing early [[74 series]] [[transistor-transistor logic|TTL]] chips. They all plugged into a custom [[backplane]], formed from three 4-slot [[system unit]]s wired together into one monolithic unit.
+
The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate mappings, to provide separate virtual address spaces for each mode.
  
−
==Internal structure==
+
An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called '''Split I+D space''' capability; this increases the memory available to the operating system, and each user, to 128 Kbytes. Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.) When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.
  
−
The KA11 is basically divided into four main sections:
+
[[Trap]] and [[interrupt vector]]s are fetched from Kernel Data space, when memory management is enabled; this allows bad physical main memory at [[absolute address]] 0 to be bypassed, if it is failing.
  
−
* Bus Interface
+
If any instruction causes a [[fault]] (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory management trap occurs.
−
* [[Data path|Data Paths]]
 
−
* [[Register]]s
 
−
* Control
 
  
−
(There is also a Console section, which allows the machine's [[front panel|front console]] to control the CPU, but it is not involved in 'normal' machine operation.)
+
===Simplified subset===
  
−
The Bus Interface and Control sections communicate with the machine's main [[bus]], the [[UNIBUS]]; only the former transfers data, the latter's connection is to allow the KA11 to serve as the 'bus arbitrator' for the UNIBUS. Only the Data Paths section can pass data to the Bus Interface section.
+
A number of the smaller PDP-11's (notably the [[PDP-11/40]], [[PDP-11/34]], [[PDP-11/60]], [[PDP-11/23]] and [[PDP-11/24]]) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).
  
−
There is a 16x16 [[register file]], of which half are used to hold the machine's [[PDP-11 architecture|general registers]]; two of the others are used for internal temporary registers (Temp and Source). A number of other internal registers (e.g. the [[Instruction Register]] and [[Bus Address Register]]) are implemented separately, to make them always available. The Register section communicates only with the Data Path section.
+
Also, there is no SSR1 [[register]] (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which [[PDP-11 architecture#Addressing modes|auto-increment]] the same register several times).
  
−
The [[condition codes]] are part of the Control section, but are generated in the Data Paths section.
+
==Registers==
  
−
===State machine===
+
The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which keep most of the information needed for memory management in page tables held in main memory, and cached in the CPU).
  
−
As noted above, the KA11 does not have microcode; instead, it uses a [[state machine]] to control the operation of the CPU. There are 5 major states:
+
===Control===
  
−
* Fetch - obtain and decode the instruction;
+
There are four registers which control the overall operation of the Memory Management Unit:
−
* Source - decode the source field of a [[PDP-11 architecture#Operands|double-operand instruction]], fetch the data, and store it in a temporary;
 
−
* Destination - decode the destination field, and obtain the data;
 
−
* Execute - use the data obtained in previous states to perform the requested operation, including writing data back to the destination;
 
−
* Service - perform special operations such as interrupts, traps, etc.
 
  
−
Each major state contains a number of minor states, as needed to perform the operations of that state (e.g. perform a bus cycle to fetch a memory word). These minor states are named ISRn (from Instruction Shift Register) for minor states associated with internal processor actions, and BSRn (from Bus Shift Register) for minor states associated with bus operations.
+
{| class="wikitable"
 +
! Address !! Name !! Function
 +
|-
 +
| 777572 || SSR0 || Control and status
 +
|-
 +
| 777574 || SSR1 || Register increment/decrement record
 +
|-
 +
| 777576 || SSR2 || Virtual address associated with the fault (usually the instruction address)
 +
|-
 +
| 777516 || SSR3 || D-space enable/disable (per mode)
 +
|}
  
−
Not all instructions pass through all 5 major states, although all do pass through 'Fetch'. 'Source' and 'Destination' are not entered if the [[PDP-11 architecture#Addressing modes|mode]] for that operand is 'Register'; only 'full' double-operand instructions (i.e. those with mode bits in the source) will enter 'Source' state.
+
The names were changed to SR0-SR3 after the 'Segmentation' term was dropped from the name; the forms MMR0-MMR3 are also occasionally met with. On the 'simplified subset' machines, SSR1 and (usually) SSR3 are not implemented (the [[KDF11 CPUs]] are an exception to the latter; see below).  
  
−
'Source' and 'Destination' are very similar, but within each, the sequence of minor states varies considerably between each of the seven [[PDP-11 architecture#Addressing modes|operand modes]] other than mode 0, direct register access (for which, as previously mentioned, the Source or Destination major state is bypassed entirely).
+
SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved). The layout of SSR0 is:
 +
{{16bit-header}}
 +
| Non-resident || Length || Read-only || Trap || colspan=2 | Unused || Enable Trap || Maintenance || Instruction Completed || colspan=2 | CPU Mode || I/D || colspan=3 | Page || Enable
 +
{{16bit-bitout}}
  
−
===Data paths===
+
When any of the first three bits (all error aborts) are set, bits 1-7, as well as SSR1 and SSR2, are frozen. On the 'simplified subset' machines, bits 12, 9, 7 and 4 are not implemented.
  
−
The [[arithmetic logic unit|ALU]] in the KA11 is an extremely simple one, unlike all other -11's; it can only perform additions.
+
SSR1 contains information about register modifications (given there in [[two's complement]]) performed during the course of an instruction, to allow those modifications to be 'backed out' if the instruction needs to be restarted after a memory management fault. Its layout is:
 +
{{16bit-header}}
 +
| colspan=5 | Change || colspan=3 | Register || colspan=5 | Change || colspan=3 | Register
 +
{{16bit-bitout}}
  
−
[[Image:LatchingMux.jpg|thumb|left|200px|Latching mux]]
+
SSR2 contains the address of the instruction which caused the memory management fault.
  
−
Each input to the adder has a three-input mux (implemented as a NOR [[gate]] of three inputs with NANDs to enable them; shown to the side); a latch formed with the output of the mux can also be fed back through the mux (i.e. as a fourth input to it). The A mux can select from register data, and complemented register and bus data; the B mux can select register and bus data.
+
SSR3 contains bits to enable Split I+D in the three modes; on machines which have [[UNIBUS map]]s, the enable for it is also here. Its layout is:
 +
{{16bit-header}}
 +
| colspan=10 | Unused || Enable UNIBUS Map || Enable 22-bit || Unused || Kernel || Supervisor || User
 +
{{16bit-bitout}}
  
−
Enabling two inputs to a mux ORs together the data in the two inputs. To perform an AND, De Morgan's theorem is used; the complemented data inputs are ORed together, and the result is again complemented; this, however, requires two passes through the ALU.
+
The 'Enable 22-bit' bit only applies on machines which support larger memories, i.e. the [[PDP-11/70]], [[PDP-11/44]], and machines with the KDF11 CPUs and [[KDJ11 CPUs]].
  
−
The complemented inputs on the A mux also allow the creation of constants; e.g. simultaneously selecting 'register' and 'complemented register' creates -1. Control of the gating for bit 0 of the A mux is independent of the gating control for bits 15-1, which allows bit 0 to be set to 0 or 1 as needed, to create the constants -2, +1, etc.
+
===PARs and PDRs===
  
−
A mux on the output allows one-bit shift/rotate operations (the original [[PDP-11 architecture#Instruction set|PDP-11 instruction set]] does not support multi-bit shifts), as well as byte swapping; the shift capability is used in other ways as well (e.g. in calculating the destinations of branch instructions, which include a word offset).
+
Each segment (up to 48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register (PAR).
  
−
===Bus interface===
+
The PAR contains the base physical address for the segment (in units of 0100/64. bytes). On machines which have only [[UNIBUS]] memory (e.g. PDP-11/40, [[PDP-11/45]], etc) these registers are 12 bits long, since the maximum amount of physical memory on these machines is 248 Kbytes. On machines which support up to 4 MBytes of physical memory (e.g. [[PDP-11/70]], [[PDP-11/44]], PDP-11/23, etc), they are 16 bits long.
  
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The DATIP (read with expected write to follow) UNIBUS cycle, especially useful for [[core memory]] (which must write the date back into a location which has just been read) when it is known that a write to a location will follow a read of it, is heavily used by the KA11.
+
The PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by the hardware), etc. The layout of the PDR is:
  
−
Reads in the Destination major state are done as DATIPs, and when the instruction reaches the Execute major state, a 'DATO#' bus cycle is used to write the data back; this is a special internal form of the DATO cycle which indicates that the address to be written to is already available in the Bus Address Register. (Since calculating the address can be a lengthy process, especially if index words or deferred modes are used, the ability to avoid re-doing that computation is very significant.)
+
{{16bit-header}}
 +
| Don't Cache || colspan=7 | Length || Trapped || Written || colspan=2 | Unused || Direction || colspan=3 | Access Control
 +
{{16bit-bitout}}
  
−
==Implementation==
+
The values of the 'Access Control' field are:
 +
{| class="wikitable"
 +
! Value !! Mode
 +
|-
 +
| 0 || Non-resident - abort all accesses
 +
|-
 +
| 1 || Read-only watched - abort on write, trap on read
 +
|-
 +
| 2 || Read-only - abort on write
 +
|-
 +
| 3 || Unused, reserved - abort all accesses
 +
|-
 +
| 4 || Read/write all watched - trap on read or write
 +
|-
 +
| 5 || Read/write watched - trap on write
 +
|-
 +
| 6 || Read/write - none
 +
|-
 +
| 7 || Unused, reserved - abort all accesses
 +
|}
 +
 
 +
On the 'simplified subset' machines, only modes 0, 2 and 6 are supported, and neither is the 'Trapped' bit (set on PDR's for memory references that trapped, on the other machines).
  
−
As previously mentioned, the CPU consisted of two and a half quad system unit backplanes (the two otherwise-unused slots were [[Small Peripheral Controller|SPC]] slots, available for any [[peripheral]]) [[wire-wrap]]ped into a single unit.
+
The 'Don't Cache' bit is only available on the [[KDJ11 CPUs]].
  
−
Most of the circuitry was on [[DEC card form factor|quad]]-height boards, but there were some duals, and a few singles. The KA11 board set comprises:
+
The addresses of the PAR/PDR sets are:
  
 
{| class="wikitable"
 
{| class="wikitable"
−
! Board !! Function
+
! Address !! Name !! Function
 +
|-
 +
| 772200 || SISD0 || Supervisor I-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772216 || SISD7 || Supervisor I-Space PDR #7
 +
|-
 +
| 772220 || SDSD0 || Supervisor D-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772236 || SDSD7 || Supervisor D-Space PDR #7
 +
|-
 +
| 772240 || SISA0 || Supervisor I-Space PAR #0
 
|-
 
|-
−
| colspan="2" style="text-align:center;" | Single
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| M823 || Codes Data
+
| 772256 || SISA7 || Supervisor I-Space PAR #7
 
|-
 
|-
−
| M825 || Power Failure and Control
+
| 772260 || SDSA0 || Supervisor D-Space PAR #0
 
|-
 
|-
−
| colspan="2" style="text-align:center;" | Dual
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| M224 (two instances) || Data Paths (8 bits; 2 latches, adder)
+
| 772276 || SDSA7 || Supervisor D-Space PAR #7
 
|-
 
|-
−
| M225 || Registers (16 bits x 16)
+
| 772300 || KISD0 || Kernel I-Space PDR #0
 
|-
 
|-
−
| M821 || Register Control
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| M822 || Flag Control
+
| 772316 || KISD7 || Kernel I-Space PDR #7
 
|-
 
|-
−
| M824 || Priority
+
| 772320 || KDSD0 || Kernel D-Space PDR #0
 
|-
 
|-
−
| colspan="2" style="text-align:center;" | Quad
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| M724 || Bus and Console Control
+
| 772336 || KDSD7 || Kernel D-Space PDR #7
 
|-
 
|-
−
| M725 || Bus Interface and IR
+
| 772340 || KISA0 || Kernel I-Space PAR #0
 
|-
 
|-
−
| M726 || IR Decode
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| M727 || State Control
+
| 772356 || KISA7 || Kernel I-Space PAR #7
 
|-
 
|-
−
| M728 || Timing and States
+
| 772360 || KDSA0 || Kernel D-Space PAR #0
 
|-
 
|-
−
| M820 || Data Path Control
+
| colspan="2" style="text-align:center;" | ...
−
|}
 
−
 
 
−
Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in [[Digital Equipment Corporation|DEC]] documentation) are:
 
−
 
 
−
{| class="wikitable"
 
−
! !! colspan="6" | Connector
 
 
|-
 
|-
−
! Slot !! A !! B !! C !! D !! E !! F
+
| 772376 || KDSA7 || Kernel D-Space PAR #7
 
|-
 
|-
−
| 1 || colspan="6" style="text-align:center;" | [[KY11-A Programmer's Console|KY11-A]]
+
| 777600 || UISD0 || User I-Space PDR #0
 
|-
 
|-
−
| 2 ||   || [[KM11 Maintenance Board|KM11]] || colspan="4" style="text-align:center;" | M727
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| 3 || Power || M823 || colspan="4" style="text-align:center;" | M728
+
| 777616 || UISD7 || User I-Space PDR #7
 
|-
 
|-
−
| 4 ||   || M825 || colspan="4" style="text-align:center;" | M726
+
| 777620 || UDSD0 || User D-Space PDR #0
 
|-
 
|-
−
| 5 || colspan="2" |   || colspan="4" style="text-align:center;" | M724
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| 6 || colspan="2" |   || colspan="4" style="text-align:center;" | M725
+
| 777636 || UDSD7 || User D-Space PDR #7
 
|-
 
|-
−
| 7 || Power ||   || colspan="4" style="text-align:center;" | M820
+
| 777640 || UISA0 || User I-Space PAR #0
 
|-
 
|-
−
| 8 || colspan="2" |   || colspan="2" style="text-align:center;" | M224 || colspan="2" style="text-align:center;" | M224
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| 9 || colspan="2" | UNIBUS termination || colspan="2" style="text-align:center;" | M822 || colspan="2" style="text-align:center;" | M821
+
| 777656 || UISA7 || User I-Space PAR #7
 
|-
 
|-
−
| 10 ||   || [[KW11-L Line Time Clock|KW11-L]] || colspan="2" style="text-align:center;" | M824 || colspan="2" style="text-align:center;" | M225
+
| 777660 || UDSA0 || User D-Space PAR #0
 
|-
 
|-
−
| 11 || Power ||   || colspan="4" style="text-align:center;" | SPC
+
| colspan="2" style="text-align:center;" | ...
 
|-
 
|-
−
| 12 || colspan="2" style="text-align:center;" | UNIBUS Out || colspan="4" style="text-align:center;" | SPC
+
| 777676 || UDSA7 || User D-Space PAR #7
 
|}
 
|}
  
 
==See also==
 
==See also==
  
−
* [[KT11-B Paging Option]]
+
* [[KT11-B Paging Option]] - DEC experiment with paging
 +
* [[KT11-C Memory Management Unit]] - the archetype
 +
 
 +
==Further reading==
 +
 +
* ''Extended Memory for the LSI-11'', [[MicroNote]] #028
  
 
==External links==
 
==External links==
  
−
* [http://www.bitsavers.org/pdf/dec/pdp11/1120/KA11_ProcessorMan.pdf KA11 processor manual]
+
* [http://www.bitsavers.org/pdf/dec/pdp11/memos/701014_Segmentation.pdf A Segmentation Scheme for the PDP-11 Family] - interesting design memo
−
* [http://www.bitsavers.org/pdf/dec/pdp11/1120/1120_SystemSchems_Feb70.pdf PDP-11/20 engineering drawings] - KA11 on pp. 3-58 of the PDF; block diagram on pg. 12
 
−
* [http://www.bitsavers.org/pdf/dec/pdp11/memos/690904_Details_of_Design_KA11.pdf Details of Design, KA11] - early memo explaining internal operation
 
−
* [http://www.bitsavers.org/pdf/dec/pdp11/memos/691023_KA11_Design_Critique.pdf KA11 Design Critique] - a retrospective memo as the machine was going into production
 
  
−
[[Category: PDP-11 UNIBUS Processors]]
+
[[Category: PDP-11s]]

Latest revision as of 17:20, 27 July 2024

PDP-11s which provide memory management use a standard PDP-11 Memory Management architecture. When memory management is enabled, the basic 64 Kbyte address space of the PDP-11 architecture is divided into 8 'segments' (the terminology used in the first version of the documentation; it was later changed to 'pages', for unknown reasons, but this is incorrrect - the functionality provided is that of segmentation, not paging).

Each segment of a virtual address space can be individually assigned to any location in physical main memory. Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 stacks, which typically grow down (from higher addresses to lower).

The CPU can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate mappings, to provide separate virtual address spaces for each mode.

An additional enhancement is that instruction and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called Split I+D space capability; this increases the memory available to the operating system, and each user, to 128 Kbytes. Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.) When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.

Trap and interrupt vectors are fetched from Kernel Data space, when memory management is enabled; this allows bad physical main memory at absolute address 0 to be bypassed, if it is failing.

If any instruction causes a fault (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory management trap occurs.

Simplified subset

A number of the smaller PDP-11's (notably the PDP-11/40, PDP-11/34, PDP-11/60, PDP-11/23 and PDP-11/24) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).

Also, there is no SSR1 register (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which auto-increment the same register several times).

Registers

The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which keep most of the information needed for memory management in page tables held in main memory, and cached in the CPU).

Control

There are four registers which control the overall operation of the Memory Management Unit:

Address Name Function
777572 SSR0 Control and status
777574 SSR1 Register increment/decrement record
777576 SSR2 Virtual address associated with the fault (usually the instruction address)
777516 SSR3 D-space enable/disable (per mode)

The names were changed to SR0-SR3 after the 'Segmentation' term was dropped from the name; the forms MMR0-MMR3 are also occasionally met with. On the 'simplified subset' machines, SSR1 and (usually) SSR3 are not implemented (the KDF11 CPUs are an exception to the latter; see below).

SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved). The layout of SSR0 is:

Non-resident Length Read-only Trap Unused Enable Trap Maintenance Instruction Completed CPU Mode I/D Page Enable
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

When any of the first three bits (all error aborts) are set, bits 1-7, as well as SSR1 and SSR2, are frozen. On the 'simplified subset' machines, bits 12, 9, 7 and 4 are not implemented.

SSR1 contains information about register modifications (given there in two's complement) performed during the course of an instruction, to allow those modifications to be 'backed out' if the instruction needs to be restarted after a memory management fault. Its layout is:

Change Register Change Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

SSR2 contains the address of the instruction which caused the memory management fault.

SSR3 contains bits to enable Split I+D in the three modes; on machines which have UNIBUS maps, the enable for it is also here. Its layout is:

Unused Enable UNIBUS Map Enable 22-bit Unused Kernel Supervisor User
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The 'Enable 22-bit' bit only applies on machines which support larger memories, i.e. the PDP-11/70, PDP-11/44, and machines with the KDF11 CPUs and KDJ11 CPUs.

PARs and PDRs

Each segment (up to 48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register (PAR).

The PAR contains the base physical address for the segment (in units of 0100/64. bytes). On machines which have only UNIBUS memory (e.g. PDP-11/40, PDP-11/45, etc) these registers are 12 bits long, since the maximum amount of physical memory on these machines is 248 Kbytes. On machines which support up to 4 MBytes of physical memory (e.g. PDP-11/70, PDP-11/44, PDP-11/23, etc), they are 16 bits long.

The PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by the hardware), etc. The layout of the PDR is:


Don't Cache Length Trapped Written Unused Direction Access Control
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The values of the 'Access Control' field are:

Value Mode
0 Non-resident - abort all accesses
1 Read-only watched - abort on write, trap on read
2 Read-only - abort on write
3 Unused, reserved - abort all accesses
4 Read/write all watched - trap on read or write
5 Read/write watched - trap on write
6 Read/write - none
7 Unused, reserved - abort all accesses

On the 'simplified subset' machines, only modes 0, 2 and 6 are supported, and neither is the 'Trapped' bit (set on PDR's for memory references that trapped, on the other machines).

The 'Don't Cache' bit is only available on the KDJ11 CPUs.

The addresses of the PAR/PDR sets are:

Address Name Function
772200 SISD0 Supervisor I-Space PDR #0
...
772216 SISD7 Supervisor I-Space PDR #7
772220 SDSD0 Supervisor D-Space PDR #0
...
772236 SDSD7 Supervisor D-Space PDR #7
772240 SISA0 Supervisor I-Space PAR #0
...
772256 SISA7 Supervisor I-Space PAR #7
772260 SDSA0 Supervisor D-Space PAR #0
...
772276 SDSA7 Supervisor D-Space PAR #7
772300 KISD0 Kernel I-Space PDR #0
...
772316 KISD7 Kernel I-Space PDR #7
772320 KDSD0 Kernel D-Space PDR #0
...
772336 KDSD7 Kernel D-Space PDR #7
772340 KISA0 Kernel I-Space PAR #0
...
772356 KISA7 Kernel I-Space PAR #7
772360 KDSA0 Kernel D-Space PAR #0
...
772376 KDSA7 Kernel D-Space PAR #7
777600 UISD0 User I-Space PDR #0
...
777616 UISD7 User I-Space PDR #7
777620 UDSD0 User D-Space PDR #0
...
777636 UDSD7 User D-Space PDR #7
777640 UISA0 User I-Space PAR #0
...
777656 UISA7 User I-Space PAR #7
777660 UDSA0 User D-Space PAR #0
...
777676 UDSA7 User D-Space PAR #7

See also

Further reading

  • Extended Memory for the LSI-11, MicroNote #028

External links

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