Difference between revisions of "KS10"
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The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier [[KL10]] [[mainframe]]. | The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier [[KL10]] [[mainframe]]. | ||
| − | + | Its [[main memory]], specific to the KS10, used [[ECC]] for error detection (and possibly correction). | |
| − | For I/O, it used a pair of [[UNIBUS]]es, driven by adapters which interfaced them to the KS10's internal bus. One was for the [[disk]]s only, the other for all other devices ([[magnetic tape]], [[asynchronous serial line]]s, etc) | + | For I/O, it used a pair of [[UNIBUS]]es, driven by adapters which interfaced them to the KS10's internal bus. One was for the [[disk]]s only, the other for all other devices ([[magnetic tape]], [[asynchronous serial line]]s, etc). |
| − | The UNIBUS which is used for the disks was run in 18-bit mode (the two parity lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an [[RH11 MASSBUS controller|RH11]], mounted in the main [[ | + | ==Internal details== |
| + | |||
| + | 8 different sets of [[Central Processing Unit|CPU]] [[register]]s were provided, to speed up [[interrupt]] handling. Separate [[page table]]s mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations. | ||
| + | |||
| + | The UNIBUS which is used for the disks was run in [[UNIBUS parity#18-bit width|18-bit mode]] (the two [[parity]] lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an [[RH11 MASSBUS controller|RH11]], mounted in the main CPU rack (although apparently on its own [[backplane]]) to drive the [[MASSBUS]] to the disks. (Only MASSBUS disks were supported, apparently both for performance reasons, and since 18-bit data storage was needed). | ||
| + | |||
| + | The [[device controller]]s on the second UNIBUS were mounted in a [[BA11-K mounting box]], mounted in the main cabinet. These included a second RH11 in DEC-supported systems, since [[Digital Equipment Corporation|DEC]] required a tape drive for loading [[diagnostic]]s; the usual choice was a [[TU45 magtape drive|TU45]] interfaced via a [[TM02 magtape controller|TM02]]. | ||
| − | == | + | ===CPU details=== |
It was built out of [[LS TTL]] [[chip]]s, along with [[AMD 2901]] 4-bit-wide bit slice chips. The CPU was on four [[DEC card form factor|super hex]] cards: | It was built out of [[LS TTL]] [[chip]]s, along with [[AMD 2901]] 4-bit-wide bit slice chips. The CPU was on four [[DEC card form factor|super hex]] cards: | ||
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* MMA - [[Dynamic RAM|DRAM]] memory array modules (2 to 8) | * MMA - [[Dynamic RAM|DRAM]] memory array modules (2 to 8) | ||
* UBA - UNIBUS adapters (2, optionally 3) | * UBA - UNIBUS adapters (2, optionally 3) | ||
| + | |||
| + | The CPU and main memory mounted in a single backplane, consisting of two 9-slot [[system unit]]s [[wire-wrap]]ped together. | ||
[[Category: PDP-10 Processors]] | [[Category: PDP-10 Processors]] | ||
Revision as of 16:55, 21 November 2019
| KS10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Introduced: | 1978 |
| Form Factor: | small mainframe |
| Word Size: | 36 bits |
| Logic Type: | LS TTL ICs |
| Design Type: | clocked synchronous microcoded |
| Microword Width: | 96 |
| Microcode Length: | 2K |
| Clock Speed: | 300 nsec (micro-cycle) |
| Cache Size: | 512 words |
| Cache Speed: | 300 nsec |
| Memory Speed: | 0.9 μsec |
| Physical Address Size: | 19 bits (some had 20) |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, ITS, TYMCOM-XX |
| Predecessor(s): | KL10 |
| Successor(s): | None |
The KS10 was the fourth and last generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier KL10 mainframe.
Its main memory, specific to the KS10, used ECC for error detection (and possibly correction).
For I/O, it used a pair of UNIBUSes, driven by adapters which interfaced them to the KS10's internal bus. One was for the disks only, the other for all other devices (magnetic tape, asynchronous serial lines, etc).
Internal details
8 different sets of CPU registers were provided, to speed up interrupt handling. Separate page tables mapped the UNIBUS address space into the KS10's main memory for DMA operations.
The UNIBUS which is used for the disks was run in 18-bit mode (the two parity lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an RH11, mounted in the main CPU rack (although apparently on its own backplane) to drive the MASSBUS to the disks. (Only MASSBUS disks were supported, apparently both for performance reasons, and since 18-bit data storage was needed).
The device controllers on the second UNIBUS were mounted in a BA11-K mounting box, mounted in the main cabinet. These included a second RH11 in DEC-supported systems, since DEC required a tape drive for loading diagnostics; the usual choice was a TU45 interfaced via a TM02.
CPU details
It was built out of LS TTL chips, along with AMD 2901 4-bit-wide bit slice chips. The CPU was on four super hex cards:
- DPE data path
- DPM data path
- CRA control store
- CRM control store
Additional super hex cards held:
- CSL - the console (driven by an Intel 8080A), and bus arbitrator
- MMC - main memory controller
- MMA - DRAM memory array modules (2 to 8)
- UBA - UNIBUS adapters (2, optionally 3)
The CPU and main memory mounted in a single backplane, consisting of two 9-slot system units wire-wrapped together.
