KS10
| KS10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Introduced: | 1978 |
| Form Factor: | small mainframe |
| Word Size: | 36 bits |
| Logic Type: | LS TTL ICs |
| Design Type: | clocked synchronous microcoded |
| Microword Width: | 96 |
| Microcode Length: | 2K |
| Clock Speed: | 300 nsec (micro-cycle) |
| Cache Size: | 512 words |
| Cache Speed: | 300 nsec |
| Memory Speed: | 0.9 μsec |
| Physical Address Size: | 19 bits (some had 20) |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, ITS |
| Predecessor(s): | KL10 |
| Successor(s): | None |
The KS10 was the fourth and last generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier KL10 mainframe.
It was built out of LS TTL chips, along with AMD 2901 4-bit-wide bit slice chips. The CPU was on four super hex cards:
- DPE data path
- DPM data path
- CRA control store
- CRM control store
Additional cards held:
- CSL - the console (driven by an Intel 8080A), and bus arbitrator
- MMC - main memory controller
- MMA - memory array modules (2 to 8)
- UBA - UNIBUS adapters (2; one for the disks, the other for everthing else)
A separate page table maps the UNIBUS address space into the KS10's main memory for DMA operations. The UNIBUS which is used for the disks is run in 18-bit mode (the two parity lines on the UNIBUS are recycled into two extra data lines), and has an RH11 to drive the MASSBUS to the disks (only MASSBUS disks are supported, since an 18-bit data path is needed).
8 different sets of CPU registers are provided, to speed up interrupt handling. The main memory uses ECC for error detection (and possibly correction).
