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• VAXstation 3200/3500
  {{InfoboxVAX-Data ...]] bus. (The [[address space]] of the [[QBUS]] was limited to 4MB, and the data section is only 16 bits wide.)
  2 KB (296 words) - 07:15, 31 January 2024
• Relocatable binary
  ...code|binary]] [[instruction]]s and data 'understood' by a given [[Central Processing Unit|CPU]]. These modules, which can be easily modified to operate at any [ In addition to the instructions (in binary form) and data, a relocatable binary module contains other information, needed for the lin
  1 KB (154 words) - 22:16, 9 October 2022
• Binary
  ...level of essentially all computers. It can also refer to numbers or other data stored in this form. ...e low-level form of a computer program which the hardware in the [[Central Processing Unit|CPU]] can interpret directly.
  407 bytes (64 words) - 18:23, 16 December 2018
• Secondary storage
  ...on it was not directly accessible to the [[Central Processing Unit|CPU]]; data in secondary storage generally had to be brought into main memory through a ...tape]], etc; these often were a bridge to prior non-electronic information-processing technologies (e.g. paper tape was used in [[teletype]]s).
  946 bytes (152 words) - 19:04, 3 May 2023
• Complex Instruction Set Computer
  ...r''' (usually abbreviated to '''CISC''') is one from a school of [[Central Processing Unit|CPU]] [[architecture]] which was the default approach until the rise o ...t generation were performance limited by the speed at which they could get data and instructions from memory; and they were also often had limited address
  2 KB (245 words) - 02:44, 3 September 2019
• Architecture
  ...(both those visible to the [[programmer]], and internal registers); the [[data path]]s which connect them all together; and the control system (usually [[
  3 KB (488 words) - 00:30, 23 October 2023
• Stack
  ...rage which is used to temporarily hold data in a 'push-down' fashion; i.e. data can be '''pushed''' onto the stack, and then '''popped''' off of it (in the Modern [[Central Processing Unit|CPU]]s generally dedicate one [[register]] to be a [[stack pointer]],
  931 bytes (164 words) - 16:20, 15 December 2018
• Honeywell 6000 series
  ...he same: a [[tightly-coupled]] [[multi-processor]], with all the [[Central Processing Unit|CPUs]] sharing access to a collection of [[multi-port memory]] units. '''Note:''' ''The data below is generally sourced from Honeywell documentation, including marketin
  12 KB (1,837 words) - 19:24, 3 January 2024
• Instruction set
  ...to the repertoire of [[instruction]]s provided by any particular [[Central Processing Unit|CPU]] [[architecture]]. ...nstructions to be able to use a [[stack]] as the source or destination for data.
  781 bytes (112 words) - 19:53, 3 June 2023
• Instruction
  ...allest unit of computation which a [[programmer]] can direct the [[Central Processing Unit|CPU]] to perform. ...U (e.g. add the contents of one [[register]] to another, or move a unit of data from a register, to main memory) - those items are instructions. (An instru
  774 bytes (119 words) - 19:50, 3 June 2023
• TOPS-10
  ...nded from the 'Monitor' OS used on the [[PDP-6]]. It provided both [[batch processing]] and [[time-sharing]] capabilities. TOPS-10 allowed programs to be separated into data and [[object code]] segments; the latter could be shared by all [[process]]
  1 KB (190 words) - 03:32, 28 November 2023
• RH11 MASSBUS controller
  ...1 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B'). ...t mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, th
  6 KB (951 words) - 15:40, 25 February 2022
• KS10
  ...he main [[backplane]]), to which are attached the [[microcode]]d [[Central Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] ada ...internal bus; the address is transferred on one cycle, and the associated data on a following cycle.
  8 KB (1,237 words) - 19:48, 14 July 2023
• PDP-15
  ...between protected and un-protected memory, and two modes for the [[Central Processing Unit|CPU]]. A memory relocation option, the KT15, with a [[base and bounds] ...r 18-bit mode]], where the two [[parity]] lines were recycled into 2 extra data lines.
  4 KB (591 words) - 13:40, 11 July 2023
• RH70 MASSBUS controller
  ...[[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). ...connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's
  2 KB (318 words) - 15:45, 25 February 2022
• Program
  * direction to move data from one place to another ...loaded into the [[main memory]] of the computer, from where the [[Central Processing Unit|CPU]] will fetch the individual [[instruction]]s of the program, and e
  1 KB (201 words) - 11:55, 4 December 2023
• PDP-9
  | caption = PDP-9 at MIT Cognitive Information Processing Group ...nt Corporation|DEC]]'s fourth 18-bit computer, and the first DEC [[Central Processing Unit|CPU]] to use [[microcode]]. A little over 400 were built. It was basic
  6 KB (801 words) - 22:14, 9 February 2024
• IBM 709
  ...ddress]]ing, and [[channel]]s (called 'Data Synchronizers' at the time). A Data Synchronizer had two channels, to each of which could be attached a [[card ...ww-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP709.html 709 Data Processing System] - IBM Archive page
  2 KB (304 words) - 02:19, 9 August 2022
• IBM 7090
  It was designed hurriedly to meet the requirements of Sylvania, the data processing subcontractor for the [[BMEWS]] missile warning [[radar]] network, which wa ...-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7090.html 7090 Data Processing System] - IBM Archive page
  2 KB (287 words) - 02:18, 9 August 2022
• IBM 7094
  ...-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7094.html 7094 Data Processing System] - IBM Archive page
  2 KB (269 words) - 02:16, 9 August 2022

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