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  • DIAGNOSTICS - PHASE 1 STARTING... DIAGNOSTICS - PHASE 1 FINISHED SUCCESSFULLY.
    15 KB (2,569 words) - 08:21, 20 May 2022
  • * [[DECnet]] V1.3 for [[VMS]] is [[DECnet#Phase II (1976)|DECnet Phase II]].
    15 KB (1,849 words) - 16:06, 20 September 2022
  • ...(= DECnet adresses) in the range 1 to 31 ([[DECnet#Phase II (1976)|DECnet Phase II]]).
    28 KB (3,686 words) - 19:40, 16 November 2023
  • NCP served DECnet Phases I to IV, but Phase V ([[DECnet-OSI]]) had its own new management program '''[[NCL]]'''. ===Phase I (1975)===
    3 KB (454 words) - 18:17, 29 September 2023
  • Phase I revision control on the 11/730 will be implemented in a manner
    38 KB (3,857 words) - 14:02, 2 July 2022
  • %AUTOGEN-I-BEGIN, GETDATA phase is beginning. %AUTOGEN-I-END, GETDATA phase has successfully completed.
    65 KB (7,949 words) - 21:58, 19 August 2023
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    36 KB (4,892 words) - 18:40, 3 July 2022
  • 2. Phase in new etch to remove wire's on module.
    118 KB (7,116 words) - 14:05, 2 July 2022
  • o New revisions of M8227 and M8228 KA780 modules. Phase 1 Phase-in to manufacturing - no field upgrades.
    70 KB (7,782 words) - 14:04, 2 July 2022
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    73 KB (9,059 words) - 20:56, 22 May 2023
  • ...option (number 4) during the "SPECIFY OPTIONS FOR THE CONFIGURATION FILE" phase. ** Phase 1 - Check Blocks and Sizes
    32 KB (4,724 words) - 22:56, 7 July 2022
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    80 KB (9,795 words) - 09:39, 10 July 2022
  • %AUTOGEN-I-BEGIN, GETDATA phase is beginning. %AUTOGEN-I-END, GETDATA phase has successfully completed.
    112 KB (13,727 words) - 18:09, 30 January 2024
  • ...45 inches per second, and data is recorded at 1600 bits per inch, using [[Phase Encoded|PE]] [[encoding]]. Use of [[ANSI]] standard format recording allows ** 1600 bit/in phase encoded ANSI compatible recording
    3 KB (475 words) - 01:01, 1 January 2024
  • ...omated tools helped to correct design bugs early. ECL technology and a two-phase clock system achieve a 45-nanosecond cycle time. [[Microcode|Micro instruct
    8 KB (1,158 words) - 03:12, 23 May 2024
  • | H7170-A | 120V 3-phase 2.8KW 300V Supply | E1 | E1 | F1 | F1 | F1 | F1 |
    239 KB (10,046 words) - 20:25, 22 May 2023
  • | M7606-ML005 F1 H2 Phase in new ROM version 1.3; Update documentation... | M7606-ML007 H2 H3 Phase in higher yield 21-20887-01 (DC333) chip; Update K-PL...
    170 KB (7,189 words) - 20:26, 22 May 2023
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    33 KB (4,919 words) - 12:31, 21 June 2023
  • ...PC registers. SM starts a new memory cycle. Processing enters the fetch phase at CMA 21. ...4<br>DEI clears the indirect addressing bit in IR4. The memory cycle read phase has put the indirect address in MB. Processing loops back to CMA 24 to sta
    11 KB (1,387 words) - 09:37, 13 August 2023
  • ...g [[Non Return to Zero Inverted|NRZI]] [[encoding]]) and 1600 BPI (using [[Phase Encoding|PE]]). The tape transport utilizes a single capstan, with twin ver
    2 KB (298 words) - 20:39, 21 April 2024

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