Difference between revisions of "KS10"
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The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier [[KL10]] [[mainframe]]. | The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier [[KL10]] [[mainframe]]. | ||
| − | It was built out of [[LS TTL]] [[chip]]s, along with [[AMD 2901]] 4-bit-wide bit slice chips. The | + | 8 different sets of CPU [[register]]s were provided, to speed up [[interrupt]] handling. The [[main memory]] used [[ECC]] for error detection (and possibly correction). |
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| + | For I/O, it used a pair of [[UNIBUS]]es, driven by adapters which interfaced them to the KS10's internal bus. One was for the [[disk]]s only, the other for all other devices ([[magnetic tape]], [[asynchronous serial line]]s, etc). A separate page table mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations. | ||
| + | |||
| + | The UNIBUS which is used for the disks was run in 18-bit mode (the two parity lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an [[RH11 MASSBUS controller|RH11]], mounted in the main [[Central Processing Unit|CPU]] cabinet to drive the [[MASSBUS]] to the disks. (Only MASSBUS disks were supported, since an 18-bit data path was needed). | ||
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| + | ==Internal details== | ||
| + | |||
| + | It was built out of [[LS TTL]] [[chip]]s, along with [[AMD 2901]] 4-bit-wide bit slice chips. The CPU was on four [[DEC card form factor|super hex]] cards: | ||
* DPE data path | * DPE data path | ||
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* CRM control store | * CRM control store | ||
| − | Additional cards held: | + | Additional super hex cards held: |
* CSL - the console (driven by an [[Intel 8080|Intel 8080A]]), and bus arbitrator | * CSL - the console (driven by an [[Intel 8080|Intel 8080A]]), and bus arbitrator | ||
| − | * MMC - | + | * MMC - main memory controller |
| − | * MMA - memory array modules (2 to 8) | + | * MMA - [[Dynamic RAM|DRAM]] memory array modules (2 to 8) |
| − | * UBA - | + | * UBA - UNIBUS adapters (2, optionally 3) |
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[[Category:DEC CPUs]] | [[Category:DEC CPUs]] | ||
Revision as of 14:43, 20 October 2017
| KS10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Introduced: | 1978 |
| Form Factor: | small mainframe |
| Word Size: | 36 bits |
| Logic Type: | LS TTL ICs |
| Design Type: | clocked synchronous microcoded |
| Microword Width: | 96 |
| Microcode Length: | 2K |
| Clock Speed: | 300 nsec (micro-cycle) |
| Cache Size: | 512 words |
| Cache Speed: | 300 nsec |
| Memory Speed: | 0.9 μsec |
| Physical Address Size: | 19 bits (some had 20) |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, ITS |
| Predecessor(s): | KL10 |
| Successor(s): | None |
The KS10 was the fourth and last generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier KL10 mainframe.
8 different sets of CPU registers were provided, to speed up interrupt handling. The main memory used ECC for error detection (and possibly correction).
For I/O, it used a pair of UNIBUSes, driven by adapters which interfaced them to the KS10's internal bus. One was for the disks only, the other for all other devices (magnetic tape, asynchronous serial lines, etc). A separate page table mapped the UNIBUS address space into the KS10's main memory for DMA operations.
The UNIBUS which is used for the disks was run in 18-bit mode (the two parity lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an RH11, mounted in the main CPU cabinet to drive the MASSBUS to the disks. (Only MASSBUS disks were supported, since an 18-bit data path was needed).
Internal details
It was built out of LS TTL chips, along with AMD 2901 4-bit-wide bit slice chips. The CPU was on four super hex cards:
- DPE data path
- DPM data path
- CRA control store
- CRM control store
Additional super hex cards held:
- CSL - the console (driven by an Intel 8080A), and bus arbitrator
- MMC - main memory controller
- MMA - DRAM memory array modules (2 to 8)
- UBA - UNIBUS adapters (2, optionally 3)
