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• OMNIBUS
  ...'''OMNIBUS''' was [[Digital Equipment Corporation|DEC]]'s [[peripheral]] [[bus]] for the later [[PDP-8 family|PDP-8]]'s; it was introduced with the [[PDP- ...ck of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.
  2 KB (325 words) - 04:52, 19 September 2021
• H777 Power Supply
  ...d for the [[PDP-11/24]] in the BA11-L box) also provided +15V/-15V for use by its [[EIA RS-232 serial line interface|RS232]] [[asynchronous serial line]] A combination of up to 3 modules, composed of [[printed circuit board|boards]] with integral [[heat sink]]s,
  3 KB (519 words) - 15:41, 10 July 2023
• QBUS backplanes
  ...width [[backplane]]s, each slot held four 'connectors', DEC's term for a [[DEC edge connector contact identification|group of edge connector pins]], denom ...[[DEC edge connector contact identification|CD connectors]] form a private bus, sometimes called the [[CD interconnect]], used to connect together board p
  4 KB (676 words) - 23:17, 6 April 2024
• KA650 Main Memory System
  ...intended to be used with the KA650 CPU, as the name might suggest. These [[DEC card form factor|quad]]-width [[printed circuit board|cards]] contain 8MB a ====Memory Control Signals Provided by the CMCTL====
  42 KB (5,491 words) - 12:55, 7 May 2024
• DQ11 NPR Synchronous Line Interface
  ...bits/second were supported by the EIA interface, and up to 1M bits/second by the current loop interface. The DQ11 has a set of 16 'shadow' registers, access to which is gained by placing the shadow register number in the appropriate bits in the DQRER, an
  8 KB (1,222 words) - 04:17, 18 February 2023
• ML11 MOS Memory System
  ...s, could hold up to 4MB in 1MB increments (composed of groups of 4 storage modules); later, the use of 64Kbx1 chips expanded the maximum to 16MB. An ML11 with | 004 ||   || MLBA || Bus Address
  5 KB (611 words) - 18:24, 14 August 2023
• UNIBUS and QBUS termination
  ...QBUS termination''' are very similar, since in [[analog]] terms the two [[bus]]es are very similar (e.g. their use of the same transceiver [[integrated c ...g termination of the otherwise un-terminated [[transmission line]]s of the bus (i.e. a [[resistor|resistance]] at the end of a transmission line that prev
  7 KB (1,202 words) - 14:32, 28 November 2023
• M7850 parity controller
  ...o error, and by 200 nsec if there is; [[cycle time]] on write is increased by 40 nsec. If an error occurs, an [[Light Emitting Diode|LED]] on the M7850 i ...the associated memory unit(s) are plugged. (Since all the relevant memory modules are hex-sized, the M7850 must go in another slot.) One M7850 can provide pa
  3 KB (434 words) - 00:07, 20 April 2024
• MS750 Memory System
  ...G|300px|thumb|right|/750 backplane from behind, showing the slots occupied by the MS750 in the centre]] * one to eight memory array modules
  2 KB (342 words) - 12:04, 28 March 2023
• VAX-11/750 & VAX-11/751 Revision Control
  | WILL BE NOTED BY AN " ** " IN THE LEFT MARGIN | the kernel and option modules, see sections 5.1 and 6.
  101 KB (10,182 words) - 14:04, 2 July 2022
• VAX-11/785 Revision Control
  DEC Standard 068. changed. This document is under ECO control and will be updated by
  118 KB (7,116 words) - 14:05, 2 July 2022
• Setting Up RIS on ULTRIX V2.0
  * Use at least two computers connected by [[LAN]]. You can either use multiple computers connected by a LAN to solve this, or do a special network setup.
  32 KB (4,724 words) - 22:56, 7 July 2022
• KA730 CPU
  ...m [[PAL]] [[integrated circuit|chips]] extensively, to fit it onto three [[DEC card form factor|hex]] boards: ...to the FPA. The internal memory bus runs from the MCT to the memory array modules.
  2 KB (234 words) - 00:54, 6 July 2022
• Extended Memory Interconnect
  ...ng|thumb|400px|rightt|A four-processor VAX 6200 system built around an XMI bus]] ...000 series]], and also used in other later [[Digital Equipment Corporation|DEC]] [[VAX]] computers, to cope with increased requirements, e.g bandwidth.
  3 KB (491 words) - 01:43, 8 May 2024
• HSC50 Hierarchical Storage Controller
  ...''' and '''HSC50 Mass Storage Server''' in [[Digital Equipment Corporation|DEC]]'s documentation) is an intelligent [[mass storage]] sub-system [[server]] ...is a [[magnetic tape]] formatter, the [[Standard Tape Interconnect]] (STI) bus is used.
  9 KB (1,370 words) - 23:47, 28 December 2023
• VSV11 Graphic System
  ...scanning a large raster array memory in the VSV11, the image is specified by a [[display program]] held in [[main memory]]. The VSV11 used [[Direct Memo ...] was not performed by re-reading the display program; rather, it was done by repetitively scanning the raster memory in the VSV11. The VSV11 was capable
  3 KB (390 words) - 12:39, 27 February 2024
• KDA50 disk controller
  ...ect#SDI Family of DSA Products|SDI disks]] to a [[QBUS]]. It uses a radial bus configuration instead of the conventional daisy-chain (serial) method; thus ...eporting both to the host and through [[Light Emitting Diode|LEDs]] on the modules minimizes repair time.
  6 KB (888 words) - 10:56, 31 August 2023
• Laser System Bus
  ...000 series]], and also used in other later [[Digital Equipment Corporation|DEC]] computers. ...s has special capabilities to support the shared access to memory required by such a system, including support for [[cache coherency]].
  3 KB (396 words) - 01:44, 8 May 2024
• VAX 85x0, 8700, 88xx, and 897x systems
  ...n three different model designations VAX 85xx, VAX 8700, and VAX 8800, the DEC internal superordinate name was "VAX 8800 Family" from the beginning: ...ement a five-stage [[pipeline]]. A high-speed memory interconnect, the NMI bus, links CPUs to memory and the I/O subsystem, which connects to VAXBI buses.
  6 KB (844 words) - 22:15, 29 April 2024
• VAX 8500/8530/8550 Revision Control
  ...| COVERED BY THIS | ...The unit revision control changes in this document will be controlled by the |-----------------|
  233 KB (10,381 words) - 20:20, 22 May 2023

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