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- This is the Computer History Wiki ('CHWiki', for short), a knowledge base about historic computers which anyone can join in order to edit! ...wledgeable people to enter their information into some kind of a knowledge base. This is however, not the relatively formalized tone and style imposed by4 KB (643 words) - 19:13, 24 April 2024
- ! Register !! Abbreviation !! Address | Bus Address Register || RKBA || 7774444 KB (563 words) - 13:33, 26 February 2023
- ...ment Corporation|DEC]], in production from 1970-1990. Although the basic [[address space]] was 16 bits, most models could hold more [[main memory]] than that, ...essentially the entire [[instruction set]], allowed it to provide a two-[[address]] instruction [[architecture]], not a simple [[load-store architecture]] li13 KB (1,949 words) - 17:37, 29 February 2024
- <!-- | physical address = 15 bits (32K words) --> | virtual address = 24 bits (optionally 32 on the Model 67)15 KB (2,167 words) - 14:58, 23 January 2024
- : ''XENIX was originally developed on a DEC Virtual Address Extension (VAX) running the Virtual Memory System (VMS) and a PDP-11 runnin ...even incorporated the elements of BSD and became the most widely installed base of any Unix variant. Talking about the different modifications of Xenix, it12 KB (1,893 words) - 19:28, 21 October 2023
- The earliest versions ran on the PDP-6, using the [[base and bounds]] [[memory management]] [[hardware]] native to that machine. Lat ...d [[front end]] [[PDP-11]]'s, their memory could be mapped into processes' address spaces, too.12 KB (1,926 words) - 21:29, 8 February 2024
- at the address given below. ical contact's address supplied without use of a post office20 KB (3,013 words) - 04:22, 10 December 2018
- address "tropix@tropix.nce.ufrj.br. base is necessary (at least) create the disk, 3 ½ "called91 KB (12,020 words) - 17:55, 13 August 2019
- use 'localaddr=addr' to specify the host address to send packets from -rtc [base=utc|localtime|date][,clock=host|vm][,driftfix=none|slew]15 KB (2,245 words) - 12:58, 27 February 2024
- qe0: DEC DELQA Ethernet Interface DEQNA-lock Mode, hardware address 08:00:2b:aa:bb:cc Copying Base System (ULTBASE400) from tape13 KB (1,865 words) - 18:41, 3 July 2022
- ...ations with segment values, the real-mode .exe header includes a far start address whose segment clearly has to be a code segment. Accordingly SST marked the10 KB (1,619 words) - 20:45, 13 January 2024
- ...es addresses and data which are 32 bits wide; the traditional minicomputer address space bound of 64K is gone. This memorandum describes the VAX-11/780 and th ...ce, intelligent console, and dramatically improved physical packaging. The address space of a process is divided into a few gigantic segments. Each segment is49 KB (7,745 words) - 14:29, 6 May 2023
- For the installed base of COMPAQ DESKPRO 386tm owners, Microsoft announced that the Windows/386 pr ...ws/386 represents a valuable extension of benefits for the large installed base of DOS and Windows applications which can only be achieved through the uniq5 KB (748 words) - 18:06, 13 January 2024
- ...change the address and recompile. Also, if the devices's interrupt vector address(es) are not currently known to the system (this is likely), then the f ...out copying. The super-block of the device has a word giving the highest address which can be allocated. For relatively small increases, this word can be42 KB (6,834 words) - 03:01, 17 January 2023
- ['''address'''] [,'''count'''] ['''command'''] [;] If '''address''' is present then '''dot''' is set to '''address'''. Initially14 KB (2,585 words) - 14:41, 26 October 2009
- ...t. Two [[DIP switch]]es, E90 and E34, configure the controller's [[bus]] [[address]] and [[interrupt vector]] (respectively). The controller is designed for [ ...]; two are read-only and write-only (respectively), and share the same bus address:3 KB (369 words) - 20:54, 31 December 2023
- ...ddress is normally 0774500; additional unit are assigned [[floating device address space|floating addresses]]. * Jumpers W1 through W12 - Address2 KB (363 words) - 15:09, 24 April 2024
- ne0 ethernet address fe:fd:00:00:00:01 at 0x300 irq 9 on isa<br> == Second boot, Base System ==27 KB (4,355 words) - 23:38, 26 March 2023
- The old 8086/8088 [[CPU]]s could address 1MB of [[RAM]] on their 20-bit [[address bus]] (2^20 is 1,048,576) and this memory is chopped up into 64KB [[segment ...f operation, protected mode, which when activated would supply a virtual [[address space]] of 1GB (1,073,741,824), and a 24bit memory bus (2^24 is 16,777,216)5 KB (920 words) - 15:27, 1 January 2019
- # Load the stack of address # Global descriptor table and the length of the initial address printed in the Register gdtr14 KB (1,991 words) - 01:23, 20 December 2018
- is to be printed as a base 10 number. special arrangements to pass to the function the address of71 KB (8,839 words) - 02:18, 17 December 2018
- add_file("base.tar", 10240); b: Base No8 KB (1,125 words) - 02:02, 18 November 2010
- could not be included in the base distribution base08 The NetBSD 0.8 base binary distribution.34 KB (5,687 words) - 18:11, 16 December 2018
- ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]], or [ The first line after the console is always assigned the address 0776500, and vector 0300. Additional lines are assigned addresses and vecto3 KB (489 words) - 01:18, 17 February 2023
- ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector. The first line after the console is always assigned the address 0776500, and vector 0300. Additional lines are assigned addresses and vecto4 KB (684 words) - 01:20, 17 February 2023
- ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when The first line after the console is always assigned the address 0776500, and vector 0300. Additional lines are assigned addresses and vecto2 KB (378 words) - 19:15, 7 July 2023
- /BASE:{address|@filename,key}6 KB (799 words) - 13:28, 19 October 2018
- -BASE:{address|address,size|@filename,key} -BASE:{address|address,size|@filename,key}10 KB (1,224 words) - 03:20, 17 December 2018
- drive (max. of 4 per host controller) with a unique address. This is three shock mounts which isolate the base casting from the frame is19 KB (2,351 words) - 03:47, 19 May 2024
- change the address and recompile. If the devices's inter- rupt vector address(es) are different from those currently57 KB (8,582 words) - 03:00, 17 January 2023
- 2.5.3.2 Effective-Address Computation 3.11.1 Address Calculation Instruction890 KB (107,817 words) - 03:20, 3 January 2024
- do not require the Communications and Data Base Managers of Operating either 512KB or 640KB in the lower address space, and 1MB above the50 KB (7,113 words) - 03:35, 17 December 2018
- secure from deliberate attack. No corporation will be willing to base its existing base of real mode applications.627 KB (92,395 words) - 03:42, 17 December 2018
- qe0: DEC DELQA Ethernet Interface DEQNA-lock Mode, hardware address 08:00:2b:04:14:02 * Base System * Kernel Config Files44 KB (6,192 words) - 09:30, 29 September 2023
- Base address:0x9000 Memory:fa040000-fa060000 fixed-address 192.168.0.67;12 KB (1,853 words) - 20:06, 10 December 2015
- X * This structure contains the output queue for the interface, its address, ... X#define ds_addr ds_ac.ac_enaddr /* hardware Ethernet address */35 KB (6,389 words) - 02:51, 16 January 2024
- interrupt address, whereas the Versatec itself has two need for copying the entire address space of the parent.113 KB (13,419 words) - 02:06, 17 December 2018
- | physical address = 18 bits (normal), 19/20 ([[Incompatible Timesharing System|ITS]] paging b | virtual address = 18 bits2 KB (298 words) - 07:28, 6 September 2023
- The [[TU58]] tape drive is connected to a DL11-type device, so the device [[address]], etc for TU58's are as for DL11's - the [[register]] addresses and [[inte ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector.7 KB (1,055 words) - 17:22, 6 February 2024
- It allows implementation of [[virtual memory]]; the [[address space]] is divided into [[page]]s, and when a reference it made to a page w ...of 64 KBytes is accessable (i.e. in the [[Central Processing Unit|CPU]]'s address space) at any one time.15 KB (2,571 words) - 22:23, 11 October 2022
- ...[[architecture]]. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '[[segment]]s' (th ...in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow9 KB (1,311 words) - 18:10, 2 July 2023
- ...ctionality: when enabled, the UNIBUS map allows 8 Kbyte blocks of UNIBUS [[address space]] to be mapped to 8 Kbyte blocks (there is no ability to limit the si ...w-order register has only 15, since the block cannot be assigned to an odd address.)2 KB (310 words) - 04:15, 7 January 2021
- ...cal [[main memory]], while the [[program|computation]] which is using that address space is running. ...ivate to that user/process. (Early [[memory management]] systems such as [[base and bounds]] [[register]]s provided this feature alone.)5 KB (876 words) - 20:01, 22 January 2024
- The scratchpad has a built-in [[address]] multiplexor, so address lines from a variety of sources are all fed directly into it; see the "Keys ...rator which checks to see whether cycles are in the 'Simple' part of the [[address space]].)31 KB (4,983 words) - 18:22, 2 July 2023
- ...choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 [[integrated circuit|chip]], which implements floating point using [[ ...y used diagnostic 'trick' is to store very small test programs in the Page Address Registers of the [[PDP-11 Memory Management]] unit. This is typically used3 KB (457 words) - 14:32, 21 February 2023
- A '''virtual address''' is an address emitted by [[object code|code]] running when it is not running on a 'bare m Originally this protection was provided by '[[base and bounds]] [[register]]s', which allowed the entire memory of a user/proc963 bytes (147 words) - 21:35, 15 December 2018
- /BASE:{address|@filename,key}6 KB (766 words) - 02:02, 17 December 2018
- /BASE:{address|@filename,key}7 KB (835 words) - 02:03, 17 December 2018
- /BASE:{address|@filename,key}7 KB (913 words) - 02:04, 17 December 2018
- | physical address = 18 bits | virtual address = 18 bits3 KB (510 words) - 07:28, 6 September 2023
- | physical address = 4 megabytes * The lower 16 registers can be used as base or index registers for addressing.3 KB (496 words) - 03:51, 20 October 2018
- ...ic [[object code]]. Rather than being in [[binary]] (expressed in whatever base), it instead uses mnemonics to indicate the [[instruction]]s (e.g. 'ADD'), ...n't need to be modified as the program is changed (changing the [[absolute address]]es at which their targets reside).1 KB (167 words) - 00:30, 20 June 2023
- ...f a pair of [[register]]s which gave the location in [[main memory]] (the 'base') of the [[user]]'s allocated memory area, and another which set a limit on ...that limit was in terms of actual main memory, or in terms of the user's [[address space]], depended on the details of the hardware implementation, and was on995 bytes (161 words) - 21:34, 15 December 2018
- | physical address = 17 bits (128K words) | virtual address = 12 bits (direct), 15 bits (indirect), 17 bits (indexed)4 KB (591 words) - 13:40, 11 July 2023
- ...ocess]] is allowed to use. In other words, it controls what the process' [[address space]] looks like. ...ich makes allocation of physical memory much simpler - unlike in earlier [[base and bounds]] memory management.1 KB (235 words) - 17:28, 8 June 2023
- ...es, the source of any given cycle). It then produced cycles to relocated [[address]]es on a separate [[Extended UNIBUS]]; the latter could hold stock EUB memo ...e PAR to use for any given memory cycle is selected based on the [[virtual address]], the CPU's current mode (Kernel, User, etc), and, for machines which supp9 KB (1,569 words) - 15:47, 6 February 2024
- | A || colspan=2 | P || colspan=3 | 1 || colspan=8 | Unused || colspan=22 | Address | colspan=3 | P || colspan=3 | S || colspan=8 | Word count || colspan=22 | Address5 KB (664 words) - 17:27, 7 November 2023
- ...e page could be independently directed to a window in the selected UNIBUS' address space, controlled by the page's mapping register: | Relocation || 16 || Base address on UNIBUS3 KB (402 words) - 17:01, 22 March 2024
- ...rating modes for the [[CPU]], "user" and "monitor" (or "executive") to the base "normal" mode (in which the machine operated ''almost'' exactly as a normal * The user's [[address space]] was divided into 8 [[segment]]s (each 2K [[word]]s long), each of w4 KB (603 words) - 14:51, 11 June 2023
- '''Swapping''' is the term for moving the contents of a [[process]]' [[address space]], as a unitary entity, back and forth between [[main memory]] and [[ ...did not support paging, i.e. those which did [[memory management]] using [[base and bounds]] [[register]]s.1 KB (185 words) - 21:38, 15 December 2018
- ...ed to the index (often through use of an [[index register]]) to give the [[address]] of the desired array element.681 bytes (105 words) - 16:21, 15 December 2018
- mov home,a ;home address = 0000 (this changes with scrolling) L0133 mov a,#10H ;move 1000 to cursor address24 KB (5,539 words) - 03:05, 27 December 2018
- In the 1980s [[Xerox]] used PUP as the base for the [[Xerox Network Services]] (XNS) protocol suite; some of the protoc ...ds to the [[Internet Protocol]] (IP) layer in TCP/IP. A full PUP [[network address]] consisted of an 8-bit network number, an 8-bit host number, and a 16-bit6 KB (926 words) - 16:27, 11 May 2023
- | physical address = 17 bits | memory mgmt = [[base and bounds]]6 KB (789 words) - 17:26, 22 January 2024
- | physical address = 18 bits (256K words) | virtual address = 18 bits3 KB (467 words) - 16:37, 11 January 2024
- ...]]es in physical [[main memory]]. This may be done in a simple way, with [[base and bounds]] [[register]]s, or the use of [[page table]]s when [[virtual me483 bytes (74 words) - 19:33, 14 December 2018
- ...SPC]] slot, along with two standard single card [[FLIP CHIP]]s, the [[M105 Address Selector]] and the [[M782 Interrupt Control]]. ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector.3 KB (400 words) - 16:21, 18 February 2023
- ...cause the DIS and basic [[instruction set]] together use the entire uROM [[address space]]. ...40-pin hybrid (two chips on one carrier) which holds the two uROMs of the base instruction set. The hybrid is 23-001B6, 23-002B6, or 23-003B6 (for M7264 E1 KB (241 words) - 21:11, 2 July 2023
- | 22-23 || x || || [[Bus Address Register|BAR]] ...codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.5 KB (773 words) - 22:42, 20 December 2023
- ...est (typing '^\' in standard V6), or by any of the error conditions (odd [[address]], etc) which cause a process abort and core dump. ...either kind), they are not contiguous in the process [[virtual address]] [[address space|space]]; the [[PDP-11 Memory Management]] separates them there.4 KB (719 words) - 12:07, 2 July 2022
- It was a microcoded CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2<sup>12</sup> words, divided into 8 blocks <li>Base instructions</li>4 KB (536 words) - 12:34, 11 October 2022
- ...trollers', with the controller used for any particular cycle selected by [[address]] bit 21. ...or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].2 KB (342 words) - 12:33, 5 November 2023
- ...trollers', with the controller used for any particular cycle selected by [[address]] bit 20. ...y enabled/disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].3 KB (407 words) - 12:40, 5 November 2023
- | colspan=15 | Unused || IE || colspan=20 | Base address The base address specifies a region in physical memory holding a word pair for each line. T2 KB (311 words) - 15:15, 24 October 2022
- ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when The first line after the console is always assigned the address 0776500, and vector 0300. Additional lines are assigned addresses and vecto3 KB (469 words) - 01:19, 17 February 2023
- * per-line current output [[buffer]] [[address]] ! Register !! Abbreviation !! Address8 KB (1,088 words) - 02:24, 19 February 2023
- ...E pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRA ...y the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.42 KB (5,491 words) - 12:55, 7 May 2024
- I/O BASE ADDRESS SELECTION ! style="text-align:left;"| Address2 KB (316 words) - 15:15, 24 April 2024
- | style="padding: 0 1em 0;" | MBOX Virtual Address Port (VAP) [[#ref_1|[1]]] | style="padding: 0 1em 0;" | Graphic Base module [[#ref_3|[3]]]51 KB (6,185 words) - 15:20, 15 January 2024
- ...a program is occupying in [[main memory]] (instead of providing [[virtual address]]es, so that the program appears to always be in the same location, every t ...hose [[Central Processing Unit|CPU]] [[architecture]] provides a limited [[address space]] - less than the amount of real memory which it is desirable to have3 KB (468 words) - 15:36, 7 November 2021
- ...[[peripheral]]s. Originally, each specific peripheral was assigned a fixed address for its registers; once the number of different device types became large, ...vices (to mark the end of each group). (Each actual group must start on an address of the required modulus; e.g. if there is one DJ11 and one DH11, the DJ11 w3 KB (441 words) - 15:44, 8 February 2023
- ...[[QBUS]]). Originally, each specific [[peripheral]] was assigned a fixed [[address]] for its vector(s); once the number of different device types became large ...mass storage]] devices, generally [[disk]]s. This probably means that the 'base' unit is assigned a fixed vector, so that [[bootstrap]]s do not have to con4 KB (540 words) - 15:43, 8 February 2023
- ...synchronous serial line]] [[peripheral|interface]] for the [[UNIBUS]]. The base unit, the '''DQ11-DA/EA''', was double-[[buffer]]ed, and used separate rece ! Register !! Abbreviation !! Address8 KB (1,222 words) - 04:17, 18 February 2023
- ! Register !! Abbreviation !! Address The [[address]]es shown are for the first DV11 in a system; additional units are normally6 KB (823 words) - 04:24, 18 February 2023
- The base unit included a [[CPU|Central Processing Unit]], a small amount of [[main m ...n code]], and an optional single byte of immediate data, or two bytes of [[address]].5 KB (814 words) - 20:05, 4 June 2023
- ...ming window, on each UNIBUS, is set by configuration [[jumper]]s. The base address of the outgoing window is set by a [[register]] in the BA11-F. ! Register !! Address3 KB (513 words) - 00:01, 14 January 2022
- ...atching; also allocation of all basic system resources ([[main memory]], [[address space]] units, etc); includes initial [[trap]] and [[interrupt]] handlers, ...BSTJ/vol62-1983/articles/bstj62-1-171.pdf The 3B20D Processor & DMERT As a Base for Telecommunications Operations] (The Bell System Technical Journal, Jan5 KB (736 words) - 21:56, 29 September 2022
- ...el, the interface consists of [[shared memory]]; one page (512 words) at [[address]] 02000 (octal). The memory has some [[meta-data]] and [[ring buffer]]s fo | Address, high 8 bits5 KB (698 words) - 08:26, 10 June 2023
- * Control store address (CSA) The base CPU does support [[floating point]], but implemented entirely in microcode;3 KB (519 words) - 03:33, 18 May 2024
- ADDRESS LINE ADDRESS:028 KB (3,686 words) - 19:40, 16 November 2023
- * MicroVMS V4.6 Base Kit === Install VMS V4.6 Base Kit ===65 KB (7,949 words) - 21:58, 19 August 2023
- MCTL0 nexus=1, address=20002000 MCTL1 nexus=2, address=2000400073 KB (9,059 words) - 20:56, 22 May 2023
- * The node data base must contain these definitions, or they must be specified in the '''ccr''' ** The [[MAC Address|Ethernet hardware address]] of the target node2 KB (341 words) - 20:02, 3 July 2022
- Copying Base System (ULTBASE030) from tape Verifying Base System (ULTBASE030)80 KB (9,795 words) - 09:39, 10 July 2022
- It must be applied to the 4.6 base kit. What do you want your DECnet address to be? [1.1]: '''1.1'''112 KB (13,727 words) - 18:09, 30 January 2024
- ...or setting their addresses. Host software defines the [[interrupt vector]] address during KDA50 initialization. ! Register !! Abbreviation !! Address6 KB (888 words) - 10:56, 31 August 2023
- ...the [[GE 600 series]] family. It is notable mostly for being the design base of the [[GE-645]], a descendant created for the [[Multics]] project (after ...hich there were no limitations on its operation, or Slave mode, in which [[base and bounds]] type [[memory management]] applied.2 KB (338 words) - 12:50, 5 January 2023
- [[Address]]es in the GE-645 were notionally 36 bits wide (it was a 36-bit machine, as ...gment-addressed PC); a Descriptor Base Register (below); and eight Address Base Registers (likewise).4 KB (588 words) - 18:00, 12 January 2024
- line1 : Connection from IP address 127.0.0.1 line 2: Connection from IP address 127.0.0.164 KB (10,642 words) - 19:18, 1 February 2024
- ...| H9400-LTN01 A1 B1 BASE MAT. WILL BE CHG'D FROM MINDEL | ...K001 - Fixed the "holes in memory" problem due to address bit 23 causing address parity problems. |233 KB (10,381 words) - 20:20, 22 May 2023
- ...-10, once properly loaded, is sufficiently general to perform the required address translation entirely in hardware. We are concerned below with the details o .... ITS itself has existed since 1966 and began life on the [[PDP-6]] as a [[base and bounds|protect and relocate]] oriented system. The development of pagin23 KB (3,961 words) - 17:58, 5 January 2024
- 16,985$ for the base computer == MicroVMS V4.0 Base Installation ==53 KB (6,333 words) - 13:43, 19 July 2023
- ...- a pair of [[base and bounds]] [[register]]s, one for each half of the [[address space]]. The BBN Pager supported splitting the address space into 512 pages, each 512 [[word]]s long; '[[user]]' and 'executive' m3 KB (457 words) - 15:38, 6 January 2024
- ...] at the [[Institute for Avanced Study]] (IAS) at Princeton (von Neumann's base institution at the time). This machine became his focus after his involveme ...bits long, and contained a 10-bit [[operation code|opcode]] and a 10-bit [[address]]. <!-- There were 16 instruction classes, each with some variants, not all16 KB (2,475 words) - 07:10, 10 April 2024