Difference between revisions of "KD11-E CPU"

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The '''KD11-E CPU''' was the first [[CPU]] version for the [[PDP-11/34]]; it consisted of two [[DEC card form factor|hex]] [[printed circuit board]]s, the M7265 Data Paths module and the M7266 Control module.
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[[Image:KD11-E M7265.jpg|250px|right|thumb|M7265 Data Paths card]]
  
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Although it supported the [[KY11-LB Programmer's Console]], including the maintainence functionality which allow the CPU's [[microcode]] to be [[single-step]]ped, it did not support the [[FP11-A Floating-Point Processor|FP11-A]] [[FP11 floating point|floating point]] unit or the [[KK11-A Cache Memory|KK11-A]] [[cache]]; a PDP-11/34 system needed the upgraded [[KD11-EA CPU]] for that.
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The '''KD11-E CPU''' was the first [[Central Processing Unit|CPU]] version for the [[PDP-11/34]]; it consisted of two [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M7265''' Data Paths module and the '''M7266''' Control module. They plugged into a modified [[Modified UNIBUS Device|MUD]] [[backplane]], the [[DD11-P backplane]], which was customized for the KD11-E.
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 +
Although it supported the [[KY11-LB Programmer's Console]], including the [[diagnostic]] functionality which allow the CPU's [[microcode]] to be [[single-step]]ped, it did not support the [[FP11-A Floating-Point Processor|FP11-A]] [[FP11 floating point|floating point]] unit or the [[KK11-A Cache Memory|KK11-A]] [[cache]]; a PDP-11/34 system needed the upgraded [[KD11-EA CPU]] for that.
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The KD11-E uses the same [[KY11-L to CPU interface]] as the other machines that use them.
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[[Image:KD11-E M7266.jpg|250px|right|thumb|M7266 Control card]]
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==Implementation==
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The KD11-E makes heavy use of [[Read-only memory#PROM|PROMs]], to hold the microcode, to control the [[arithmetic logic unit|ALU]], provide [[trap]] [[address]]es, and for [[instruction]] decoding. The latter is partially accomplished in microcode, but with extensive assistance from an Instruction Decoder largely implemented in PROMs. The latter has several functional sub-units:
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* DOP Decoder, double-[[operand]] instructions
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* SOP Decoder, single-operand instructions
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* Branch Decoder, [[branch]] instructions
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* Operate Decoder, [[condition codes]] instructions
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The Instruction Decoder also checks for illegal instructions, and illegal [[PDP-11 architecture#Addressing modes|addressing modes]] on otherwise-legal instructions.
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The microcode is 48 [[bit]]s wide, stored in 12 512x4 PROMs:
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{| class="wikitable"
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! Chip !! [[DEC part number]] !! Bits !! Function
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|-
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| E97/E94|| 23-021A9 || 24-27 || B, BX, OVX CTL
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|-
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| E98/E95 || 23-022A9 || 28-31 || SSMUX CTL, AMUX CTL
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|-
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| E99/E96 || 23-020A9 || 20-23 || FUNC CODE 01-03
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|-
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| E100/E97 || 23-023A9 || 32-35 || BUT BITS
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|-
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| E102/E111 || 23-025A9 || 40-43 || FORCE K, BUT SERV, PREV, FORCE RSV1
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|-
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| E103/E112 || 23-024A9 || 36-9 || SPA SRC SEL0-1, SPA DST SEL0-1
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|-
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| E104/E113 || 23-026A9 || 44-47 || ROM SPA 00-03
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|-
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| E105/E114 || 23-019A9 || 16-19 || LOAD BA, LONG CYC, AUX SETUP, FUNC CODE 04
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|-
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| E106/E115 || 23-018A9 || 12-15 || BUF DAT TRAN, BUF C0/C1, ENAB MAINT
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|-
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| E107/E116 || 23-017A9 || 8-11 || MPC00, Misc Control
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|-
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| E108/E117 || 23-016A9 || 4-7 || MPC01-04
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|-
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| E109/E118 || 23-015A9 || 0-3 || MPC05-08
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|}
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''Note:'' The chip numbers in the KD11-E FMPS (MP0004) are given with two differing assignments; the 'Control Word' diagram (pg. 1 of the 'KD11-E Flow Diagrams') gives one set of numbers (the second, in the table above); the actual prints of the M7266 use another (given as the first in the table above).
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Instruction Decoder uses 13 PROMs, of differing sizes:
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 +
{| class="wikitable"
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! Chip !! DEC part number !! Size !! Function
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|-
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| E52 || 23-175A2 || 256x4 || Trap Decoder
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|-
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| E53 || 23-162A2 || 256x4 || Reset/Trap Decode
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|-
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| E58 || 23-174A2 || 256x4 || SOP Decode
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|-
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| E59 || 23-173A2 || 256x4 || SOP Microbranch
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|-
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| E60 || 23-161A2 || 256x4 || SOP ALU Control
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|-
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| E61 || 23-170A2 || 256x4 || Rotate/Shift ALU Control
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|-
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| E62 || 23-176A2 || 256x4 || Op Branch
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|-
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| E67 || 23-014A9 || 512x4 || Condition Codes
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|-
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| E68 || 23-172A2 || 256x4 || DOP Decoder
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|-
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| E69 || 23-171A2 || 256x4 || DOP Decoder
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|-
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| E71 || 23-A22A2 || 256x4 || Branch Decoder
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|-
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| E73 || 23-110A1 || 32x8 || [[PDP-11 Extended Instruction Set|EIS]] Decoder
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|-
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| E81 || 23-107A1 || 32x8 || DOP ALU Control
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|}
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The CPU stores its [[general register]]s, and some temporary internal [[register]]s used by the microcode, in a [[register file]] (the 'scratchpad'):
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 +
{| class="wikitable"
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! Register !! Function
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|-
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| R0-R5 || General register
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|-
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| R6 || Kernel mode [[Stack Pointer]]
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|-
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| R7 || [[Program Counter]]
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|-
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| R10 || Temporary storage
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|-
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| R11 || Unused
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|-
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| R12 || Temporary storage - copy of [[Processor Status Word|PSW]]; destination [[address]]; destination [[operand]]
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|-
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| R13 || Temporary storage - destination address; multiply/divide operand
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|-
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| R14 || Unused
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|-
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| R15 || Temporary storage - [[interrupt vector]]
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|-
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| R16 || User mode Stack Pointer
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|-
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| R17 || Temporary storage
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|}
  
 
==KY11-LB Interface==
 
==KY11-LB Interface==
  
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The interface to the KY11-LB is carried over two 10-wire [[flat cable]]s connected to [[Berg connector]] headers (denominated J1 and J2) on the M7266 module.
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The main functionality of the KY11-B [[KY11-L to CPU interface|is performed]] over the UNIBUS, and a pair of backplane lines.
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The microcode diagnostic interface to the KY11-LB is carried over two 10-wire [[flat cable]]s with female [[Berg connector]]s connected to [[wire-wrap]] pin groups (denominated J1 and J2) in the upper left corner of the M7266 module.
  
 
==See also==
 
==See also==
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* [[KD11-E/EA microcode]]
 
* [[KD11-E/EA microcode]]
  
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{{semi-stub}}
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==External links==
  
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{{PDP-11}}
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* [http://www.bitsavers.org/pdf/dec/pdp11/1134/EK-KD11E-TM-001_KD11-E_Central_Processor_Maintenance_Manual_Dec76.pdf KD11-E central processor maintenance manual] (EK-KD11E-TM-001)
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* [http://www.bitsavers.org/pdf/dec/pdp11/1134/MP00082_1134_Vol2_Sep76.pdf 11/34 Vol. 2 Field Maintenance Print Set] (MP00082) - KD11-E is covered on pp. 41-62 of the PDF
  
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[[Category: PDP-11 Processors]]
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[[Category: PDP-11 UNIBUS Processors]]
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[[Category: UNIBUS Processors]]
 

Latest revision as of 01:23, 6 December 2022

M7265 Data Paths card

The KD11-E CPU was the first CPU version for the PDP-11/34; it consisted of two hex printed circuit boards, the M7265 Data Paths module and the M7266 Control module. They plugged into a modified MUD backplane, the DD11-P backplane, which was customized for the KD11-E.

Although it supported the KY11-LB Programmer's Console, including the diagnostic functionality which allow the CPU's microcode to be single-stepped, it did not support the FP11-A floating point unit or the KK11-A cache; a PDP-11/34 system needed the upgraded KD11-EA CPU for that.

The KD11-E uses the same KY11-L to CPU interface as the other machines that use them.

M7266 Control card

Implementation

The KD11-E makes heavy use of PROMs, to hold the microcode, to control the ALU, provide trap addresses, and for instruction decoding. The latter is partially accomplished in microcode, but with extensive assistance from an Instruction Decoder largely implemented in PROMs. The latter has several functional sub-units:

  • DOP Decoder, double-operand instructions
  • SOP Decoder, single-operand instructions
  • Branch Decoder, branch instructions
  • Operate Decoder, condition codes instructions

The Instruction Decoder also checks for illegal instructions, and illegal addressing modes on otherwise-legal instructions.

The microcode is 48 bits wide, stored in 12 512x4 PROMs:

Chip DEC part number Bits Function
E97/E94 23-021A9 24-27 B, BX, OVX CTL
E98/E95 23-022A9 28-31 SSMUX CTL, AMUX CTL
E99/E96 23-020A9 20-23 FUNC CODE 01-03
E100/E97 23-023A9 32-35 BUT BITS
E102/E111 23-025A9 40-43 FORCE K, BUT SERV, PREV, FORCE RSV1
E103/E112 23-024A9 36-9 SPA SRC SEL0-1, SPA DST SEL0-1
E104/E113 23-026A9 44-47 ROM SPA 00-03
E105/E114 23-019A9 16-19 LOAD BA, LONG CYC, AUX SETUP, FUNC CODE 04
E106/E115 23-018A9 12-15 BUF DAT TRAN, BUF C0/C1, ENAB MAINT
E107/E116 23-017A9 8-11 MPC00, Misc Control
E108/E117 23-016A9 4-7 MPC01-04
E109/E118 23-015A9 0-3 MPC05-08

Note: The chip numbers in the KD11-E FMPS (MP0004) are given with two differing assignments; the 'Control Word' diagram (pg. 1 of the 'KD11-E Flow Diagrams') gives one set of numbers (the second, in the table above); the actual prints of the M7266 use another (given as the first in the table above).

Instruction Decoder uses 13 PROMs, of differing sizes:

Chip DEC part number Size Function
E52 23-175A2 256x4 Trap Decoder
E53 23-162A2 256x4 Reset/Trap Decode
E58 23-174A2 256x4 SOP Decode
E59 23-173A2 256x4 SOP Microbranch
E60 23-161A2 256x4 SOP ALU Control
E61 23-170A2 256x4 Rotate/Shift ALU Control
E62 23-176A2 256x4 Op Branch
E67 23-014A9 512x4 Condition Codes
E68 23-172A2 256x4 DOP Decoder
E69 23-171A2 256x4 DOP Decoder
E71 23-A22A2 256x4 Branch Decoder
E73 23-110A1 32x8 EIS Decoder
E81 23-107A1 32x8 DOP ALU Control

The CPU stores its general registers, and some temporary internal registers used by the microcode, in a register file (the 'scratchpad'):

Register Function
R0-R5 General register
R6 Kernel mode Stack Pointer
R7 Program Counter
R10 Temporary storage
R11 Unused
R12 Temporary storage - copy of PSW; destination address; destination operand
R13 Temporary storage - destination address; multiply/divide operand
R14 Unused
R15 Temporary storage - interrupt vector
R16 User mode Stack Pointer
R17 Temporary storage

KY11-LB Interface

The main functionality of the KY11-B is performed over the UNIBUS, and a pair of backplane lines.

The microcode diagnostic interface to the KY11-LB is carried over two 10-wire flat cables with female Berg connectors connected to wire-wrap pin groups (denominated J1 and J2) in the upper left corner of the M7266 module.

See also

External links

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