Difference between revisions of "ITS machine configurations"

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The configuration of the various [[Incompatible Timesharing System‎‎]] [[time-sharing]] [[PDP-10]] [[mainframe]]s at [[MIT]] (in the [[MIT Artificial Intelligence Laboratory|AI Lab]], where it was born, and in [[MIT Laboratory for Computer Science|LCS]], only other organization to run it 'in production') are given here. They were all physically in [[Technology Square]].
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The configuration of the various [[Incompatible Timesharing System]] [[time-sharing]] [[PDP-10]] [[mainframe]]s at [[MIT]] (in the [[MIT Artificial Intelligence Laboratory|AI Lab]], where it was born, and in [[MIT Laboratory for Computer Science|LCS]], only other organization to run it 'in production') are given here. They were all physically in [[Technology Square]].
  
 
==AI PDP-6==
 
==AI PDP-6==
 +
 +
* The first [[PDP-6]] at MIT. At first, in only had 16KW of [[core memory]]. A 256KW [[Fabritek Core Memory]] was delivered summer 1966, but not fully working until a year later.  When [[time-sharing]] moved to the newer PDP-10, the PDP-6 was reduced to the 16KW memory again.
 +
* One console teletype.
 +
* In summer 1966, the teletype logic was modified by Tom Knight to support four more teletypes.
 +
* [[GE Datanet 760]] with four CRT consoles.
 +
* MAR and one-proceed to support debugging under time-sharing.
 +
* Briefly, Analex disk drive.
 +
* [[Data Disc]] M-6 disk drives.
 +
* IBM 2311 disk interface.
  
 
==DM PDP-6==
 
==DM PDP-6==
 +
 +
* 32K core memory.
  
 
==AI KA10==
 
==AI KA10==
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The AI machine was the first [[KA10]] at MIT. It was initially installed as a 'slave' processor to the AI PDP-6 in a tightly-coupled [[multi-processor]]; later the two machines swapped roles. It was the first KA10 there to support [[virtual memory]] (an MIT custom modification).
 
The AI machine was the first [[KA10]] at MIT. It was initially installed as a 'slave' processor to the AI PDP-6 in a tightly-coupled [[multi-processor]]; later the two machines swapped roles. It was the first KA10 there to support [[virtual memory]] (an MIT custom modification).
  
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* Eventually, 512KW of [[core memory]]: the 256KW [[Fabritek Core Memory]] moby, and another 256KW [[Ampex ARM10]]. Later they both (I think) went away, and HIC added a memory box that used [[CADR]] memory boards.
+
* Eventually, 512KW of core memory: the 256KW [[Fabritek Core Memory]] moby, and another 256KW [[Ampex ARM10]]. Later they both (I think) went away, and HIC added a memory box that used [[CADR]] memory boards.
 
* [[Systems Concepts DC-10]] - disk controller
 
* [[Systems Concepts DC-10]] - disk controller
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** 8 x Calcomp drives
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** 8 x [[CalComp Model 215 Disk Drive|Calcomp 215]] drives
 
* [[TM10 Magnetic Tape Control|TM10A]]
 
* [[TM10 Magnetic Tape Control|TM10A]]
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** [[TU10]]?
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** [[TU20 Tape Transport|TU20]]
 
* [[Rubin 10-11 interface]]
 
* [[Rubin 10-11 interface]]
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** TV-11
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** TV-11 [[PDP-11/10]]
 
*** [[Knight TV system]]
 
*** [[Knight TV system]]
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** XGP-11
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** XGP-11 [[PDP-11/20]]
 
*** [[MIT UNIBUS XGP interface|XGP interface]]
 
*** [[MIT UNIBUS XGP interface|XGP interface]]
 
**** [[Xerox Graphics Printer‎|XGP]]
 
**** [[Xerox Graphics Printer‎|XGP]]
−
** CHAOS-11
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** CHAOS-11 PDP-11/10
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*** [[Chaosnet interface‎|CH11]]
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*** 2 x [[Chaosnet interface‎|CH11]]'s
 
*** [[UNIBUS Experimental Ethernet interface]]
 
*** [[UNIBUS Experimental Ethernet interface]]
−
* [[1822 interface]]
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* DH [[1822 interface]]
 
* [[Systems Concepts DK-10]]
 
* [[Systems Concepts DK-10]]
 
* TK10 TTY scanner
 
* TK10 TTY scanner
 +
 +
The 'Arpanet Resources Handbook' gives the speed of the two mobies as 2.8 μseconds and 1.1 μseconds; the former seems to be the Fabritek, so the other must be the Ampex.
  
 
==DM KA10==
 
==DM KA10==
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* Its [[DF10 Data Channel|DF10]]
 
* Its [[DF10 Data Channel|DF10]]
 
* [[TM10 Magnetic Tape Control|TM10B]]
 
* [[TM10 Magnetic Tape Control|TM10B]]
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** [[TU20]]?
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** [[TU20 Tape Transport|TU20A]]
 
* Its DF10 (or did it share the other one?)
 
* Its DF10 (or did it share the other one?)
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* Haverty [[1822 interface]]
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* Metcalfe DH 1822 interface
 
* Morton serial line box
 
* Morton serial line box
  
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* 4 x 128KW MD10's
 
* 4 x 128KW MD10's
 
* RP10
 
* RP10
−
** 4? x RP03's
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** 4 x RP03's
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** 4 x Calcomp
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** 4 x Calcomp 215's
 
* Its DF10
 
* Its DF10
 
* TM10A
 
* TM10A
−
** [[TU20]]?
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** TU20
−
* 1822 interface
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* DH 1822 interface
 
* eventually, a [[CH10]]
 
* eventually, a [[CH10]]
  
 
==MC KL10==
 
==MC KL10==
  
 +
[[Image:MIT-MC-kludge.jpg|thumb|right|300px|MC processor, with KL-UDGE to the left.]]
 
The CPU was a stock Model A; it ran custom [[microcode]], though, to implement the 'MIT paging box'. The [[main memory]] and [[channel]]s were also 100% stock. Also:
 
The CPU was a stock Model A; it ran custom [[microcode]], though, to implement the 'MIT paging box'. The [[main memory]] and [[channel]]s were also 100% stock. Also:
  
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* Its DF10
 
* Its DF10
 
* TM10B
 
* TM10B
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** Some sort of high-end DEC magtape drive
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** [[TU41]]
 
* Its DF10
 
* Its DF10
 
* A [[DTE20 Ten-Eleven Interface|DTE20]]
 
* A [[DTE20 Ten-Eleven Interface|DTE20]]
 
** A [[PDP-11/40]], the '[[front end]]' -11
 
** A [[PDP-11/40]], the '[[front end]]' -11
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*** A bunch of serial lines, I think a [[DH11 asynchronous serial line interface|DH11]]
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*** Two [[DH11 asynchronous serial line interface|DH11]]'s
 
*** A [[TC11 DECtape controller|TC11]] - which I'm not sure ITS supported
 
*** A [[TC11 DECtape controller|TC11]] - which I'm not sure ITS supported
 
* A [[DL10 PDP-11 Data Link|DL10]]
 
* A [[DL10 PDP-11 Data Link|DL10]]
 
** Another PDP-11/40, the 'IO-11'
 
** Another PDP-11/40, the 'IO-11'
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*** A DH11
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*** DH11
 +
*** [[Gould 5200]] - later moved over to Plasma
 
*** Later, a Trident controller
 
*** Later, a Trident controller
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**** Initially one, eventually three Trident T-300 drives
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**** Initially one, eventually three [[Trident disk drives|Trident T-300 drives]]
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*** Eventually a CH11
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*** Eventually two CH11's
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* 'KL-UDGE' LH [[1822 interface]] (maybe a clock, too)
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* 'KL-UDGE' LH 1822 interface (maybe a clock, too)
  
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==AI KS10==
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==KS10's==
  
−
The [[KS10]]'s were all pretty stock, hardware-wise; they also ran custom microcode. Also:
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[[File:AI+MC_KS10s.jpg|350px|thumb|right|The AI (left) and MC (probably; perhaps ML) KS10s]]
 +
 
 +
The [[KS10]]'s were all pretty stock, hardware-wise; like the KL10, they also ran custom microcode.
 +
 
 +
===AI KS10===
  
 
* Disk [[RH11 MASSBUS controller]]
 
* Disk [[RH11 MASSBUS controller]]
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* Tape RH11
 
* Tape RH11
 
** [[TM03 magtape controller|TM03]]
 
** [[TM03 magtape controller|TM03]]
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** Some sort of drive
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*** [[TU77 Magnetic Tape Transport|TU77]]
 
* [[LH-DH/11 Local/Distant Host Controller]]
 
* [[LH-DH/11 Local/Distant Host Controller]]
 
* CH11
 
* CH11
 
* [[DZ11 asynchronous serial line interface|DZ11]]
 
* [[DZ11 asynchronous serial line interface|DZ11]]
  
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==MC KS10==
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===MC KS10===
  
 
No tape drive; [[backup]]s must have been done over the [[Chaosnet]].
 
No tape drive; [[backup]]s must have been done over the [[Chaosnet]].
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* DZ11
 
* DZ11
  
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==ML KS10==
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===ML KS10===
  
 
* Disk RH11
 
* Disk RH11
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* 4 x DZ11
 
* 4 x DZ11
  
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==MD KS10==
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===MD KS10===
  
 
* Disk RH11
 
* Disk RH11
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* CH11
 
* CH11
 
* 4 x DZ11
 
* 4 x DZ11
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 +
==See also==
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 +
* [[:File:Mc2019.jpg|MC's console]]
  
 
==External links==
 
==External links==
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** [https://www.computerhistory.org/collections/catalog/102803892 Knight TV Controller] - at short wall end
 
** [https://www.computerhistory.org/collections/catalog/102803892 Knight TV Controller] - at short wall end
 
** [https://www.computerhistory.org/collections/catalog/102803897 MC KL-10] - several images
 
** [https://www.computerhistory.org/collections/catalog/102803897 MC KL-10] - several images
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*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-01-acc.jpg CPU]
 
 
*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-04-acc.jpg One wing] - MF10's; also RH10 and its DF10 at the far end
 
*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-04-acc.jpg One wing] - MF10's; also RH10 and its DF10 at the far end
 
*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-03-acc.jpg Memories] - ARM10 on right, with MF10's behind
 
*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-03-acc.jpg Memories] - ARM10 on right, with MF10's behind
 
*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-02-acc.jpg The other wing] - from right, the TM10, its DF10, the DL10, the 'I/O-11' (in blank cabinet), and the first Trident
 
*** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-02-acc.jpg The other wing] - from right, the TM10, its DF10, the DL10, the 'I/O-11' (in blank cabinet), and the first Trident
 +
* [https://github.com/PDP-10/its/wiki/Hardware-info-from-David-Moon Hardware info from David Moon]
 
* [https://github.com/PDP-10/its/issues/1232 The Magic Switch]
 
* [https://github.com/PDP-10/its/issues/1232 The Magic Switch]
  
 
[[Category: PDP-10 Users]]
 
[[Category: PDP-10 Users]]

Latest revision as of 02:15, 17 November 2024

The configuration of the various Incompatible Timesharing System time-sharing PDP-10 mainframes at MIT (in the AI Lab, where it was born, and in LCS, only other organization to run it 'in production') are given here. They were all physically in Technology Square.

AI PDP-6

  • The first PDP-6 at MIT. At first, in only had 16KW of core memory. A 256KW Fabritek Core Memory was delivered summer 1966, but not fully working until a year later. When time-sharing moved to the newer PDP-10, the PDP-6 was reduced to the 16KW memory again.
  • One console teletype.
  • In summer 1966, the teletype logic was modified by Tom Knight to support four more teletypes.
  • GE Datanet 760 with four CRT consoles.
  • MAR and one-proceed to support debugging under time-sharing.
  • Briefly, Analex disk drive.
  • Data Disc M-6 disk drives.
  • IBM 2311 disk interface.

DM PDP-6

  • 32K core memory.

AI KA10

The AI machine was the first KA10 at MIT. It was initially installed as a 'slave' processor to the AI PDP-6 in a tightly-coupled multi-processor; later the two machines swapped roles. It was the first KA10 there to support virtual memory (an MIT custom modification).

The 'Arpanet Resources Handbook' gives the speed of the two mobies as 2.8 μseconds and 1.1 μseconds; the former seems to be the Fabritek, so the other must be the Ampex.

DM KA10

Another KA10, with a Systems Concepts DM-10 paging box, and also:

  • 2 x 128KW MD10's
  • a collection of other DEC early memory boxes (MA10's and/or MB10's) totalling 256KW
  • RP10
  • Its DF10
  • TM10B
  • Its DF10 (or did it share the other one?)
  • Metcalfe DH 1822 interface
  • Morton serial line box

ML KA10

Another KA10 with a DM-10, and also:

  • 4 x 128KW MD10's
  • RP10
    • 4 x RP03's
    • 4 x Calcomp 215's
  • Its DF10
  • TM10A
    • TU20
  • DH 1822 interface
  • eventually, a CH10

MC KL10

MC processor, with KL-UDGE to the left.

The CPU was a stock Model A; it ran custom microcode, though, to implement the 'MIT paging box'. The main memory and channels were also 100% stock. Also:

KS10's

The AI (left) and MC (probably; perhaps ML) KS10s

The KS10's were all pretty stock, hardware-wise; like the KL10, they also ran custom microcode.

AI KS10

MC KS10

No tape drive; backups must have been done over the Chaosnet.

  • Disk RH11
    • RP06
  • LH-DH/11
  • CH11
  • DZ11

ML KS10

  • Disk RH11
    • RP06
  • CH11
  • 4 x DZ11

MD KS10

  • Disk RH11
  • CH11
  • 4 x DZ11

See also

External links

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