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  • '''Phase Encoding''' (usually given as the acronym, '''PE''') is an [[encoding]] tec
    1 KB (248 words) - 16:25, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:16, 12 February 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:21, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:22, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:23, 20 April 2024

Page text matches

  • ==='''Phase I''' (1974)=== ==='''Phase II''' (1976)===
    17 KB (2,405 words) - 17:43, 13 January 2024
  • |7.1||1981 December||First release of RSTS/E supporting DECnet Phase III. |9.3||1986 December||First release of RSTS/E supporting DECnet Phase IV.
    14 KB (2,134 words) - 16:06, 3 May 2023
  • '''Setting up DECnet phase IV on VMS''' is a fairly straightforward procedure. Note: Before setting up any system I recommend you read up on [[DECnet Phase IV basics]].
    3 KB (447 words) - 22:03, 17 August 2022
  • The bus BDAL17 line is driven during the data read phase of a read cycle to indicate that the addressed entity (usually main memory)
    13 KB (2,043 words) - 23:27, 14 January 2024
  • <!-- | power consumption = 660 VA per phase (running); 3300 VA per phase(starting) -->
    3 KB (492 words) - 00:27, 15 August 2023
  • ...the end) and a [[sync]] bit. A spare set of 3 timing tracks, recorded in [[phase]] with the primaries, provided redundancy for the 3 primaries..
    1 KB (212 words) - 22:14, 14 August 2023
  • ...e redundant VSS pin, and requring a two-phase clock input instead of a one-phase clock input and two clock outputs, room was made to include four signals P0
    8 KB (1,369 words) - 17:59, 25 June 2021
  • HECnet is basically a DECnet phase IV network. Currently, the main router is a PDP-11
    3 KB (507 words) - 12:05, 4 March 2022
  • The recording density, of either 1600 bpi (using [[Phase Encoding|PE]] [[encoding]]) or 800 bpi (using [[Non Return to Zero Inverted
    2 KB (230 words) - 03:37, 22 April 2024
  • 1) How would you typically debug the kernel during the development phase?
    28 KB (4,805 words) - 18:01, 29 February 2024
  • ...By 1954 NUSSE was considered sufficiently stable to go to the operational phase, and was moved to the ''Norwegian Computing Centre'' ([[NCC]]).
    4 KB (647 words) - 20:59, 18 March 2024
  • We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes
    13 KB (2,064 words) - 18:04, 5 August 2017
  • We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes
    14 KB (2,318 words) - 06:15, 1 September 2018
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    16 KB (2,460 words) - 12:02, 6 September 2021
  • IBM will phase out of OS/2 altogether, one way or another. Note that they
    21 KB (3,783 words) - 03:41, 17 December 2018
  • *** [https://multicians.org/phase-one.html Phase One]
    9 KB (1,331 words) - 17:05, 7 March 2024
  • == PCI phase == This phase is trickey as you have to do a lot of foot work, but I find the PCI stuff w
    8 KB (1,323 words) - 01:27, 21 January 2023
  • And we'll be into the GUI phase of the install. Since we've got an AMD PCnet driver in the floppy drive we
    5 KB (947 words) - 11:21, 9 June 2023
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    13 KB (1,865 words) - 18:41, 3 July 2022
  • We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as
    6 KB (1,042 words) - 22:50, 1 May 2022
  • -c Suppress the loading phase of the compilation, and
    4 KB (707 words) - 14:59, 26 October 2009
  • -c Suppresses the loading phase of the compilation, as
    3 KB (432 words) - 17:28, 26 October 2009
  • Several; the non-obvious one is `Phase error', which means
    4 KB (626 words) - 18:36, 26 October 2009
  • We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes
    14 KB (2,267 words) - 16:59, 5 April 2010
  • We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes
    15 KB (2,380 words) - 18:46, 28 October 2020
  • ...[[PDP-11]] and [[VAX]] computers. Its recording density of 1600 bpi used [[Phase Encoding|PE]] [[encoding]], and it used the [[Pertec tape interface]].
    3 KB (355 words) - 14:55, 22 April 2024
  • # For example 0 x07 is normal, black white; 0 x70 is reversed - phase, black white
    14 KB (1,991 words) - 01:23, 20 December 2018
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    2 KB (225 words) - 04:17, 17 December 2018
  • during this phase... :-)
    25 KB (3,017 words) - 18:47, 13 January 2024
  • And we'll be into the GUI phase of the install.
    6 KB (997 words) - 11:22, 9 June 2023
  • Powered by a single-phase AC:
    6 KB (853 words) - 00:41, 2 January 2024
  • ...s of WD. By the way, rk-shnyh drives three-phase (!) Food, they have three-phase spindle motor akkurat ... The fact that the CMEA countries flogged PDP-11,
    1 KB (229 words) - 07:45, 29 October 2022
  • The TU78 supported two data formats: [[Phase Encoding]] (PE) or [[Group Coded Recording]] (GCR). Bit density wss 1600 bi
    2 KB (313 words) - 22:25, 21 April 2024
  • <!-- | power consumption = 660 VA per phase (running); 3300 VA per phase(starting) -->
    4 KB (533 words) - 17:08, 15 August 2023
  • | power consumption = 660 VA per phase (running); 3300 VA per phase (starting, 10 seconds max)
    2 KB (297 words) - 00:39, 15 August 2023
  • The recording density, of either 1600 bpi (using [[Phase Encoding|PE]] [[encoding]]) or 6250 bpi (using [[Group Coded Recording|GCR]
    3 KB (409 words) - 20:32, 23 April 2024
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    5 KB (848 words) - 07:12, 2 February 2016
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    57 KB (8,582 words) - 03:00, 17 January 2023
  • Intel provides field systems engineering services for any phase of your In the second phase of address transformation, the 80386 transforms a
    890 KB (107,817 words) - 03:20, 3 January 2024
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    6 KB (835 words) - 13:57, 29 May 2020
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    44 KB (6,192 words) - 09:30, 29 September 2023
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    7 KB (1,100 words) - 07:32, 2 February 2016
  • We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes
    13 KB (2,077 words) - 16:30, 7 August 2017
  • * &phi;1: The Phase 1 output from the two-phase non-overlapping clock of the processor * <u>&phi;2</u>: The inverted Phase 2 output from the two-phase non-overlapping clock of the processor, used to indicate the presence of va
    6 KB (1,084 words) - 16:55, 16 February 2024
  • *11 - Non-Simple reference (phase 1) *12 - Non-Simple reference (phase 0)
    15 KB (2,571 words) - 22:23, 11 October 2022
  • * PGM(13) (10-1): Window access (phase 1)? * PGM(14) (10-1): Window access (phase 0)?
    31 KB (4,983 words) - 18:22, 2 July 2023
  • ...pe density = 800 bpi ([[Non Return to Zero Inverted|NRZI]])<br>1600 bpi ([[Phase Encoded|PE]])
    5 KB (729 words) - 17:48, 20 April 2024
  • ...(125 IPS). It can handle 800 bits/inch ([[NRZI]]) and 1600 bits/inch (PE - Phase Encoded).
    2 KB (366 words) - 18:41, 22 May 2022
  • ...r second). It can handle 800 bits/inch ([[NRZI]]) and 1600 bits/inch (PE - Phase Encoded).
    2 KB (345 words) - 18:27, 22 May 2022
  • ...ne-independent intermediate language called OCODE, generated by the second phase, into the target machine's [[object code]]. Porting the compiler involved writing a new third phase; compiling that with the existing compiler on the host machine, producing a
    3 KB (542 words) - 07:42, 20 June 2023
  • | power consumption = 660 VA per phase (running); 3300 VA per phase (starting, 10 seconds max)
    2 KB (284 words) - 19:38, 23 December 2023
  • | power consumption = 660 VA per phase (running); 3300 VA per phase(starting)
    2 KB (233 words) - 20:45, 10 February 2024
  • ...ss Found || Clock Polarity || DMA Enable || Data Track || Address Track || Phase Lock || Address Mark || Data Mark || Clock Track
    3 KB (372 words) - 03:14, 10 December 2021
  • ...core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.
    2 KB (325 words) - 04:52, 19 September 2021
  • * 861-A - 110V two-phase, 4-prong twist plug NEMA L14-20P * 861-B - 220V single-phase, 3-prong twist plug NEMA L6-20P
    1 KB (176 words) - 04:14, 16 June 2022
  • on a 9 Track, 1600 BPI Phase Encoded Tape-Drive (i.e. TE16,
    49 KB (4,759 words) - 09:21, 27 February 2023
  • ...t was an order of magnitude faster than the existing [[KA10]]. The design phase was finished and projected to meet the goal, but at that point [[Defense Ad
    1 KB (180 words) - 21:48, 6 January 2024
  • ..., two flip-flops will add between 50ns and 100ns of delay depending on the phase relationship of the incoming bus grant with the clock, well within the spec
    21 KB (3,685 words) - 04:35, 28 November 2023
  • ...nally designed by [[Digital Equipment Corporation|DEC]] for the [[DECnet]] Phase I network [[protocol suite]], in 1974. It was retained in later versions of
    5 KB (747 words) - 18:15, 29 September 2023
  • == Phase 1 / tape boot ==
    5 KB (716 words) - 04:20, 31 August 2021
  • DIAGNOSTICS - PHASE 1 STARTING... DIAGNOSTICS - PHASE 1 FINISHED SUCCESSFULLY.
    15 KB (2,569 words) - 08:21, 20 May 2022
  • * [[DECnet]] V1.3 for [[VMS]] is [[DECnet#Phase II (1976)|DECnet Phase II]].
    15 KB (1,849 words) - 16:06, 20 September 2022
  • ...(= DECnet adresses) in the range 1 to 31 ([[DECnet#Phase II (1976)|DECnet Phase II]]).
    28 KB (3,686 words) - 19:40, 16 November 2023
  • NCP served DECnet Phases I to IV, but Phase V ([[DECnet-OSI]]) had its own new management program '''[[NCL]]'''. ===Phase I (1975)===
    3 KB (454 words) - 18:17, 29 September 2023
  • Phase I revision control on the 11/730 will be implemented in a manner
    38 KB (3,857 words) - 14:02, 2 July 2022
  • %AUTOGEN-I-BEGIN, GETDATA phase is beginning. %AUTOGEN-I-END, GETDATA phase has successfully completed.
    65 KB (7,949 words) - 21:58, 19 August 2023
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    36 KB (4,892 words) - 18:40, 3 July 2022
  • 2. Phase in new etch to remove wire's on module.
    118 KB (7,116 words) - 14:05, 2 July 2022
  • o New revisions of M8227 and M8228 KA780 modules. Phase 1 Phase-in to manufacturing - no field upgrades.
    70 KB (7,782 words) - 14:04, 2 July 2022
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    73 KB (9,059 words) - 20:56, 22 May 2023
  • ...option (number 4) during the "SPECIFY OPTIONS FOR THE CONFIGURATION FILE" phase. ** Phase 1 - Check Blocks and Sizes
    32 KB (4,724 words) - 22:56, 7 July 2022
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    80 KB (9,795 words) - 09:39, 10 July 2022
  • %AUTOGEN-I-BEGIN, GETDATA phase is beginning. %AUTOGEN-I-END, GETDATA phase has successfully completed.
    112 KB (13,727 words) - 18:09, 30 January 2024
  • ...45 inches per second, and data is recorded at 1600 bits per inch, using [[Phase Encoded|PE]] [[encoding]]. Use of [[ANSI]] standard format recording allows ** 1600 bit/in phase encoded ANSI compatible recording
    3 KB (475 words) - 01:01, 1 January 2024
  • ...ed tools helped to correct design bugs early. [[ECL]] technology and a two-phase clock system achieve a 45-nanosecond cycle time. [[Microcode|Micro instruct
    6 KB (844 words) - 22:15, 29 April 2024
  • | H7170-A | 120V 3-phase 2.8KW 300V Supply | E1 | E1 | F1 | F1 | F1 | F1 |
    239 KB (10,046 words) - 20:25, 22 May 2023
  • | M7606-ML005 F1 H2 Phase in new ROM version 1.3; Update documentation... | M7606-ML007 H2 H3 Phase in higher yield 21-20887-01 (DC333) chip; Update K-PL...
    170 KB (7,189 words) - 20:26, 22 May 2023
  • ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
    33 KB (4,919 words) - 12:31, 21 June 2023
  • ...PC registers. SM starts a new memory cycle. Processing enters the fetch phase at CMA 21. ...4<br>DEI clears the indirect addressing bit in IR4. The memory cycle read phase has put the indirect address in MB. Processing loops back to CMA 24 to sta
    11 KB (1,387 words) - 09:37, 13 August 2023
  • ...g [[Non Return to Zero Inverted|NRZI]] [[encoding]]) and 1600 BPI (using [[Phase Encoding|PE]]). The tape transport utilizes a single capstan, with twin ver
    2 KB (298 words) - 20:39, 21 April 2024
  • '''Phase Encoding''' (usually given as the acronym, '''PE''') is an [[encoding]] tec
    1 KB (248 words) - 16:25, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:16, 12 February 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:17, 12 February 2024
  • ...(using [[Non Return to Zero Inverted|NRZI]] encoding) or 1600 bpi (using [[Phase Encoding|PE]]).
    1 KB (197 words) - 18:24, 12 February 2024
  • * [[Phase Encoding]]
    1 KB (157 words) - 16:27, 20 April 2024
  • ...y the STC 3650E model. It supported 9-track operation at 1600 bpi (using [[Phase Encoding|PE]] encoding) or 6250 bpi (using [[Group Coded Recording|GCR]] en
    1 KB (191 words) - 00:14, 13 February 2024
  • | F, G, H || Phase of [[instruction]] execution
    4 KB (607 words) - 22:47, 1 April 2024
  • ...; executed in that order. A few instructions could be executed in the left phase only, and one in the right only; such limitations are given in the table be ! Group !! Opcode !! Name !! Page !! Bits !! Phase !! Brief description !! Comment
    16 KB (2,475 words) - 07:10, 10 April 2024
  • | Ec, Rc || Instruction phase
    7 KB (1,005 words) - 12:24, 2 April 2024
  • ...rack operation at 1600 and 6250 BPI. The TA78 supports two data formats: [[Phase Encoding]] (PE) or [[Group Coded Recording]] (GCR). Bit density is 1600 bit
    2 KB (356 words) - 07:40, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:21, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:22, 20 April 2024
  • #Redirect [[Phase Encoding]]
    28 bytes (3 words) - 18:23, 20 April 2024
  • ...rack operation at 1600 and 6250 BPI. The TA79 supports two data formats: [[Phase Encoding]] (PE) or [[Group Coded Recording]] (GCR). Bit density is 1600 bit
    2 KB (341 words) - 22:22, 21 April 2024
  • The TU79 supported two data [[encoding]]s: [[Phase Encoding]] (PE) or [[Group Coded Recording]] (GCR). Bit density wass 1600 b
    3 KB (397 words) - 21:58, 21 April 2024
  • The recording density, of either 1600 bpi (using [[Phase Encoding|PE]] [[encoding]]) or 6250 bpi (using [[Group Coded Recording|GCR]
    2 KB (304 words) - 21:26, 25 April 2024

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