Difference between revisions of "VAX 9000 series"

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(Hardware: cooling)
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The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
 
The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
  
* [[VAX 9000 Model 200 series]]
+
* [[VAX 9000 Model 2x0]]
 
** [[VAX 9000 Model 210]]
 
** [[VAX 9000 Model 210]]
* [[VAX 9000 Model 400 series]]
+
* [[VAX 9000 Model 4x0]]
 
** [[VAX 9000 Model 410]] - single-CPU
 
** [[VAX 9000 Model 410]] - single-CPU
 
** [[VAX 9000 Model 420]] - double-CPU
 
** [[VAX 9000 Model 420]] - double-CPU

Revision as of 18:03, 22 May 2023

The VAX 9000 series was a high-performance VAX, described by DEC as a 'mainframe computer'. They were built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled multi-processors with up to 4 CPUs. Main memory was also connected to the SCU.

The CPUs were heavily pipelined, and were built from ECL gate arrays. The performance levels in the line ranged from 30 to 108 VUPs; the VAX 9000s supported vector processing. A 'service processor unit' (SPU) containing four MicroVAX II units acted as a front end; it was primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.

The VAX 9000 used the XMI as its I/O bus; up to 4 were possible in the largest systems. Models in the series included:

The 200 group and the 400 group differ primarily in their physical packaging and available configurations.

Operating systems offered for them included VMS and Ultrix (VAXELN was supported only on the SPU).

Hardware

The CPU was built out of Multi-Chip Units (MCUs). Each CPU was implemented with 13 MCUs, with each MCU containing several ECL macrocell arrays, which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.

The 200 group is air-cooled; the 400 group also uses water-cooling.

External links