Difference between revisions of "VAX 9000 series"

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The '''VAX 9000 series''' was a high-performance [[VAX]] built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled [[multi-processor]]s with up to 4 [[Central Processing Unit|CPUs]]. The CPU was heavily [[pipeline]]d, and was built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line range from 30 to 108 [[VUP]]s. [[Main memory]] is connected to the SCU.
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The '''VAX 9000 series''' was a high-performance [[VAX]], described by [[Digital Equipment Corporation|DEC]] as a '[[mainframe]] computer'. They were built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled [[multi-processor]]s with up to 4 [[Central Processing Unit|CPUs]]. [[Main memory]] is also connected to the SCU.
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The CPUs were heavily [[pipeline]]d, and were built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line range from 30 to 108 [[VUP]]s; the VAX 9000 supported [[vector processing]]. A 'service processor unit' (SPU) containing four [[MicroVAX II]] units acted as a [[front end]]; it primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.
  
 
The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
 
The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
  
* [[VAX 9000 model 200]]
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* [[VAX 9000 Model 200 series]]
** [[VAX 9000 model 210]]
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** [[VAX 9000 Model 210]]
* [[VAX 9000 model 400]]
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* [[VAX 9000 Model 400 series]]
** [[VAX 9000 model 410]] - single-CPU
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** [[VAX 9000 Model 410]] - single-CPU
** [[VAX 9000 model 410]] - double-CPU
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** [[VAX 9000 Model 420]] - double-CPU
** [[VAX 9000 model 410]] - triple-CPU
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** [[VAX 9000 Model 430]] - triple-CPU
 
** [[VAX 9000 model 440]] - quadruple-CPU
 
** [[VAX 9000 model 440]] - quadruple-CPU
  
The 200 group and the 400 group differ primarily in their physical packaging.
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The 200 group and the 400 group differ primarily in their physical packaging and available configurations.
  
[[Operating system]]s offered for them included [[VMS]] and [[Ultrix]] ([[VAXELN]] was supported only on the service processor of a VAX 9000 system).
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[[Operating system]]s offered for them included [[VMS]] and [[Ultrix]] ([[VAXELN]] was supported only on the SPU).
  
 
==Hardware==
 
==Hardware==
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** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-9000S-SI-001_VAX_9000_System_Introduction_May90.pdf VAX 9000 Family System Introduction] (EK-9000S-SI-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-9000S-SI-001_VAX_9000_System_Introduction_May90.pdf VAX 9000 Family System Introduction] (EK-9000S-SI-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf VAX 9000 Family System Technical Description] (EK-KA90S-TD-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf VAX 9000 Family System Technical Description] (EK-KA90S-TD-001)
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* [http://vtda.org/docs/computing/DEC/VAX/EB-N0776-57-90_VAX9000LeasingProgram.pdf The VAX 9000 Leasing Program] (EB-N0776-57-90)
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* ''VAX 9000 Series'', [http://www.dtjcd.vmsresource.org.uk/pdfs/dtj_v02-04_1990.pdf Volume 2 Number 4] - [[Digital Technical Journal]] issue about the 9000 Family
  
 
{{Nav VAX}}
 
{{Nav VAX}}
  
 
[[Category: VAXen]]
 
[[Category: VAXen]]

Revision as of 13:24, 30 March 2023

The VAX 9000 series was a high-performance VAX, described by DEC as a 'mainframe computer'. They were built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled multi-processors with up to 4 CPUs. Main memory is also connected to the SCU.

The CPUs were heavily pipelined, and were built from ECL gate arrays. The performance levels in the line range from 30 to 108 VUPs; the VAX 9000 supported vector processing. A 'service processor unit' (SPU) containing four MicroVAX II units acted as a front end; it primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.

The VAX 9000 used the XMI as its I/O bus; up to 4 were possible in the largest systems. Models in the series included:

The 200 group and the 400 group differ primarily in their physical packaging and available configurations.

Operating systems offered for them included VMS and Ultrix (VAXELN was supported only on the SPU).

Hardware

The CPU was built out of Multi-Chip Units (MCUs). Each CPU was implemented with 13 MCUs, with each MCU containing several ECL macrocell arrays, which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.

External links