Difference between revisions of "VAX 9000 series"

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The '''VAX 9000 series''' was a high-end [[VAX]] built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled [[multi-processor]]s with up to 4 [[Central Processing Unit|CPUs]]. The CPU was heavily [[pipeline]]d, and was built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line range from 30 to 108 [[VUP]]s. [[Main memory]] is connected to the SCU.
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The '''VAX 9000''' was a high-performance [[Emitter-coupled logic|ECL]]-based [[VAX]].
  
The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
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==Hardware==
  
* [[VAX 9000 model 200]]
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The [[Central Processing Unit|CPU]] was built out of MCUs, or Multi-Chip Units.
** [[VAX 9000 model 210]]
 
* [[VAX 9000 model 400]]
 
** [[VAX 9000 model 410]] - single-CPU
 
** [[VAX 9000 model 410]] - double-CPU
 
** [[VAX 9000 model 410]] - triple-CPU
 
** [[VAX 9000 model 440]] - quadruple-CPU
 
  
The 200 group and the 400 group differ primarily in their physical packaging.
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Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic. The [[gate array]]s were fabricated in Motorola's "MOSAIC III" process, a [[bipolar]] process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.  
  
[[Operating system]]s offered for them included [[VMS]] and [[Ultrix]] ([[VAXELN]] was supported only on the service processor of a VAX 9000 system).
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{{stub}}
 
 
{{semi-stub}}
 
 
 
==External links==
 
 
* [http://www.bitsavers.org/pdf/dec/vax/9000/ VAX 9000] - documentation at [[Bitsavers]]
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-9000S-SI-001_VAX_9000_System_Introduction_May90.pdf VAX 9000 Family System Introduction] (EK-9000S-SI-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf VAX 9000 Family System Technical Description] (EK-KA90S-TD-001)
 
  
 
{{Nav VAX}}
 
{{Nav VAX}}
  
[[Category: VAXen]]
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[[Category: DEC VAX systems]]

Revision as of 14:05, 29 March 2023

The VAX 9000 was a high-performance ECL-based VAX.

Hardware

The CPU was built out of MCUs, or Multi-Chip Units.

Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.