Difference between revisions of "VAX 9000 series"

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The '''VAX 9000 series''' was a high-performance [[VAX]] built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled [[multi-processor]]s with up to 4 [[Central Processing Unit|CPUs]]. The CPU was heavily [[pipeline]]d, and was built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line range from 30 to 108 [[VUP]]s. [[Main memory]] is connected to the SCU.
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The '''VAX 9000 series''' was a high-performance [[VAX]], described by [[Digital Equipment Corporation|DEC]] as a '[[mainframe]] computer'. They were built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled [[multi-processor]]s with up to 4 [[Central Processing Unit|CPUs]]. [[Main memory]] was also connected to the SCU.
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The CPUs were heavily [[pipeline]]d, and were built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line ranged from 30 to 108 [[VUP]]s; the VAX 9000s also supported [[vector processing]]. A 'service processor unit' (SPU) containing four [[MicroVAX II]] units acted as a [[front end]]; it was primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.
  
 
The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
 
The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
  
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* [[VAX 9000 model 200]]
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* [[VAX 9000 Model 2x0]]
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** [[VAX 9000 model 210]]
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** [[VAX 9000 Model 210]]
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* [[VAX 9000 model 400]]
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* [[VAX 9000 Model 4x0]]
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** [[VAX 9000 model 410]] - single-CPU
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** [[VAX 9000 Model 410]] - single-CPU
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** [[VAX 9000 model 410]] - double-CPU
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** [[VAX 9000 Model 420]] - double-CPU
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** [[VAX 9000 model 410]] - triple-CPU
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** [[VAX 9000 Model 430]] - triple-CPU
 
** [[VAX 9000 model 440]] - quadruple-CPU
 
** [[VAX 9000 model 440]] - quadruple-CPU
  
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The 200 group and the 400 group differ primarily in their physical packaging.
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The 2x0 group and the 4x0 group differ primarily in their physical packaging and available configurations.
  
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[[Operating system]]s offered for them included [[VMS]] and [[Ultrix]] ([[VAXELN]] was supported only on the service processor of a VAX 9000 system).
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[[Operating system]]s offered for them included [[VMS]] and [[Ultrix]] ([[VAXELN]] was supported only on the SPU).
  
 
==Hardware==
 
==Hardware==
  
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The CPU was built out of Multi-Chip Units (MCUs). Each CPU was implemented with 13 MCUs, with each MCU containing several ECL macrocell arrays, which contained the CPU [[logic]]. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a [[bipolar]] process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.  
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The CPU was built out of Multi-Chip Units (MCUs). Each CPU was implemented with 13 MCUs, with each MCU containing several ECL macrocell arrays, which contained the CPU [[logic]]. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a [[bipolar]] process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.
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The 200 group is air-cooled; the 400 group also uses water-cooling.
  
 
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* [http://www.bitsavers.org/pdf/dec/vax/9000/ VAX 9000] - documentation at [[Bitsavers]]
 
* [http://www.bitsavers.org/pdf/dec/vax/9000/ VAX 9000] - documentation at [[Bitsavers]]
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** [http://www.bitsavers.org/pdf/dec/vax/9000/Aquarius_Aridus_Prelim_Info_Package_May88.pdf AQUARIUS/ARIDUS Preliminary Information Package] - detailed examination of the VAX 9000 systems hardware
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-9000S-SI-001_VAX_9000_System_Introduction_May90.pdf VAX 9000 Family System Introduction] (EK-9000S-SI-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-9000S-SI-001_VAX_9000_System_Introduction_May90.pdf VAX 9000 Family System Introduction] (EK-9000S-SI-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf VAX 9000 Family System Technical Description] (EK-KA90S-TD-001)
 
** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf VAX 9000 Family System Technical Description] (EK-KA90S-TD-001)
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* [http://vtda.org/docs/computing/DEC/VAX/EB-N0776-57-90_VAX9000LeasingProgram.pdf The VAX 9000 Leasing Program] (EB-N0776-57-90)
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* ''VAX 9000 Series'', [http://www.dtjcd.vmsresource.org.uk/pdfs/dtj_v02-04_1990.pdf Volume 2 Number 4] - [[Digital Technical Journal]] issue about the 9000 Family
  
 
{{Nav VAX}}
 
{{Nav VAX}}
  
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[[Category: VAXen]]
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[[Category: VAX Mainframes]]
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[[Category: VAX Families]]
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[[Category: VAX 9000 Systems]]

Latest revision as of 17:45, 20 May 2024

The VAX 9000 series was a high-performance VAX, described by DEC as a 'mainframe computer'. They were built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled multi-processors with up to 4 CPUs. Main memory was also connected to the SCU.

The CPUs were heavily pipelined, and were built from ECL gate arrays. The performance levels in the line ranged from 30 to 108 VUPs; the VAX 9000s also supported vector processing. A 'service processor unit' (SPU) containing four MicroVAX II units acted as a front end; it was primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.

The VAX 9000 used the XMI as its I/O bus; up to 4 were possible in the largest systems. Models in the series included:

The 2x0 group and the 4x0 group differ primarily in their physical packaging and available configurations.

Operating systems offered for them included VMS and Ultrix (VAXELN was supported only on the SPU).

Hardware

The CPU was built out of Multi-Chip Units (MCUs). Each CPU was implemented with 13 MCUs, with each MCU containing several ECL macrocell arrays, which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.

The 200 group is air-cooled; the 400 group also uses water-cooling.

External links


v • d • e VAX Computers and Operating Systems
VAX-11/7xx (including VAX 86x0) - VAX-11/780 • VAX-11/785 • VAX-11/750 • VAX-11/730 • VAX 8600 • VAX 8650

VAX 8000 series (excluding VAX 86x0, above) - VAX 82xx/83xx series • VAX 85xx/87xx/88xx series

MicroVAXen (many types also come in VAXserver and VAXstation models) - MicroVAX I • MicroVAX II
MicroVAX 2000 • MicroVAX 3100 • MicroVAX 3300/3400 • MicroVAX 3500/3600 • MicroVAX 3800/3900

VAXstation Series - VAXstation I • VAXstation II
VAXstation 3100 • VAXstation 3200/3500 • VAXstation 3520/3540 • VAXstation 4000 • VAXstation 8000

Late Model VAXen - VAX 4000 series • VAX 6000 series • VAX 7000 series • VAX 9000 series • VAX 10000 series

Special Purpose VAXen - VAXft series • rtVAX series • Infoserver series

Clones - CM 1700 • TPA-11/580

Operating Systems: VMS • VAXELN • ULTRIX • BSD UNIX

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