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• DEC Modules by bus
  == [[VAX 9000 series|VAX 9000]] Modules == == [[DEC 4000]] Modules ==
  51 KB (6,185 words) - 15:20, 15 January 2024

Page text matches

• QBUS
  ...the [[UNIBUS]] general system [[bus]] from [[Digital Equipment Corporation|DEC]]. It was widely used in later [[PDP-11]]s and smaller [[VAX]]en. ...US added support for block transfers, to increase the transfer rate of the bus.
  13 KB (2,043 words) - 23:27, 14 January 2024
• PDP-11/70
  | bus arch= [[UNIBUS]]/[[MASSBUS]]/memory bus ...ability to support up to 4 Mbytes of [[main memory]] via a new Main Memory Bus, and changes to the CPU to allow access to that much memory
  5 KB (729 words) - 23:43, 29 February 2024
• Digital Equipment Corporation
  '''Digital Equipment Corporation''', or '''DEC''', was a large computer company (at one time, the second-largest in the wo ...an old wool mill in Maynard, Massachusetts. The original product line was modules, [[System Module]]s. Once those were established, they started producing co
  5 KB (624 words) - 19:19, 19 March 2024
• VAX-11/730
  | BUS-UNIBUS = 1 @ 1.5MB/s [[#ref_1|[1]]] ...ge architecture, the [[Central Processing Unit|CPU]] was shrunk to three [[DEC card form factor|hex]] boards. The machine seems to have been most popular
  5 KB (711 words) - 20:49, 19 May 2024
• MicroVAX I
  | BUS-Qbus = 1 @ 3.3MB/s ...Digital Equipment Corporation|DEC]]. It used the [[QBUS]] as its primary [[bus]] between the [[Central Processing Unit|CPU]] (the [[KD32 CPU]]) and [[main
  10 KB (1,543 words) - 02:27, 7 May 2024
• M782 Interrupt Control
  ...versions '''M7820''' and '''M7821''') is a [[Digital Equipment Corporation|DEC]] [[FLIP CHIP]] which implements the '[[interrupt]] control' function for t ...ars that many of them were attempts to get rid of [[race]] issues in the [[bus grant|grant]]-passing [[arbiter|arbitration]] circuity, which is often quit
  5 KB (820 words) - 04:04, 28 November 2023
• UDA50 Disk Controller
  It uses a radial bus configuration instead of the conventional daisy-chain (serial) method; thus It consists of two [[DEC card form factor|hex]] (8.5” by 15.6”) cards, which a mounted in a UNIBUS [[backplane]] of a [[PDP-11]] o
  6 KB (980 words) - 10:55, 31 August 2023
• NetBSD 0.9 announcement
  (also via AFS by the path: by whether or not it has a file named FIXED in the
  29 KB (4,794 words) - 18:15, 16 December 2018
• TU10 DECmagtape
  ...ve contains a fair amount of [[electronics]], in the form of [[FLIP CHIP]] modules in a 19" wide [[wire-wrap]] [[backplane]] (mounted fore and aft in the driv ...]); they also convert the Positive bus from the controller to the Negative bus native to the TU10. The Master and Slave variants use the same wire-wrap ba
  9 KB (1,330 words) - 01:11, 10 February 2024
• INTEL 80386 PROGRAMMER'S REFERENCE MANUAL
  9.6.1.3 Flags Usage by Interrupt Procedure 14.8.1 Bus Lock
  890 KB (107,817 words) - 03:20, 3 January 2024
• User:Dugo/My sandbox
  You build the configuration dependent modules. This is not something I'm fast with (yet). ...of goodies. It is still being catalogued, bagged, mirrored and taged, but by the
  25 KB (3,983 words) - 02:05, 11 April 2019
• MM11-L core memory
  * G110 - [[DEC card form factor|hex-width]] memory control logic and data channels ...arity]] variant of the MM11-L, the '''MM11-LP'''; parity versions (denoted by a 'P' suffix) were available for all of the above. The MM11-LP added a dual
  5 KB (841 words) - 07:14, 25 March 2022
• CD interconnect
  ...variant thereof) is the name given to the 'bus' which is present on the [[DEC edge connector contact identification|C and D connectors]] of a [[QBUS#Back It is not actually a full [[bus]] (i.e. a given pin is not connected to 'all' instances of that pin, in eve
  3 KB (524 words) - 16:15, 22 June 2023
• KT11-B Technical Manual
  ...tems Option, the [[KT11-B Paging Option|KT11-B]] does not have the usual [[DEC]] Technical Manual. This page attempts to provide at least the high-level p ...t, and low bits - i.e. addresses within a page - from the incoming address bus).
  31 KB (4,983 words) - 18:22, 2 July 2023
• MJ11 memory system
  ...PDP-11/70]]. It was 32 bits wide, to interface to the -11/70's Main Memory Bus, and provided byte [[parity]] (4 bits/double-[[word]]). Read, Write, and Ex ...ck modules), and the '''MJ11-B''' (which used 64KB modules). Both kinds of modules had to be installed in pairs (since they were 16 bits wide, and the MJ11 de
  5 KB (865 words) - 03:22, 6 February 2024
• MK11 memory system
  ...11/70]]. It was 32 [[bit]]s wide, to interface to the -11/70's Main Memory Bus, and provided [[Error-correcting code|ECC]] (7 bits/double-[[word]]), which * the MK11-B (which used 32KB and 64KB [[MS11-K MOS memory]] array modules)
  8 KB (1,276 words) - 03:23, 6 February 2024
• DR11-B parallel interface
  ...cles on the bus, perform read-modify-write bus cycles, or do block 'burst' bus transfers. ...''not'' buffered, and must be held valid for the duration of the resultant bus cycle.
  5 KB (766 words) - 03:15, 25 November 2022
• VAX 7000 series
  ...[VAX Bus Interconnect|VAXBI]] buses, and 8 [[VME]] buses; at least one XMI bus was required. ...two 2GB memory boards, but in this case only 3.5GB would actually be used by [[OpenVMS]] (the remaining 0.5GB of physical address space being required f
  2 KB (297 words) - 00:42, 7 May 2024
• RH11 MASSBUS controller
  ...l; it uses the M9724-YA card, which has an ECO modifying the operation of 'Bus Hog' mode (see below). ...e start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s.
  6 KB (951 words) - 15:40, 25 February 2022
• KS10
  ...f the earlier [[PDP-6]] architecture) from [[Digital Equipment Corporation|DEC]]. It was intended as a small, low-cost entry model, not as a replacement f The KS10 is organized around a [[synchronous]] [[bus]] (carried only on the main [[backplane]]), to which are attached the [[mic
  8 KB (1,237 words) - 19:48, 14 July 2023
• RH70 MASSBUS controller
  ...e [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). ...in memory (although the RH70's access to the main memory bus is controlled by the cache). A write to a main memory location which is stored in the cache
  2 KB (318 words) - 15:45, 25 February 2022
• OMNIBUS
  ...'''OMNIBUS''' was [[Digital Equipment Corporation|DEC]]'s [[peripheral]] [[bus]] for the later [[PDP-8 family|PDP-8]]'s; it was introduced with the [[PDP- ...ck of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.
  2 KB (325 words) - 04:52, 19 September 2021
• H777 Power Supply
  ...d for the [[PDP-11/24]] in the BA11-L box) also provided +15V/-15V for use by its [[EIA RS-232 serial line interface|RS232]] [[asynchronous serial line]] A combination of up to 3 modules, composed of [[printed circuit board|boards]] with integral [[heat sink]]s,
  3 KB (519 words) - 15:41, 10 July 2023
• Talk:KL10
  ...such a doc would have been useful BITD; for people who already know the S-Bus, read that, and you're done), but it looks like we're going to have to read ...at in the KL10-A (the table shows the KL10-A with "No" for "Int Chan" - C Bus and RH20s, I assume).
  17 KB (2,818 words) - 12:17, 3 April 2024
• QBUS backplanes
  ...width [[backplane]]s, each slot held four 'connectors', DEC's term for a [[DEC edge connector contact identification|group of edge connector pins]], denom ...[[DEC edge connector contact identification|CD connectors]] form a private bus, sometimes called the [[CD interconnect]], used to connect together board p
  4 KB (676 words) - 23:17, 6 April 2024
• KA650 Main Memory System
  ...intended to be used with the KA650 CPU, as the name might suggest. These [[DEC card form factor|quad]]-width [[printed circuit board|cards]] contain 8MB a ====Memory Control Signals Provided by the CMCTL====
  42 KB (5,491 words) - 12:55, 7 May 2024
• DQ11 NPR Synchronous Line Interface
  ...bits/second were supported by the EIA interface, and up to 1M bits/second by the current loop interface. The DQ11 has a set of 16 'shadow' registers, access to which is gained by placing the shadow register number in the appropriate bits in the DQRER, an
  8 KB (1,222 words) - 04:17, 18 February 2023
• ML11 MOS Memory System
  ...s, could hold up to 4MB in 1MB increments (composed of groups of 4 storage modules); later, the use of 64Kbx1 chips expanded the maximum to 16MB. An ML11 with | 004 ||   || MLBA || Bus Address
  5 KB (611 words) - 18:24, 14 August 2023
• UNIBUS and QBUS termination
  ...QBUS termination''' are very similar, since in [[analog]] terms the two [[bus]]es are very similar (e.g. their use of the same transceiver [[integrated c ...g termination of the otherwise un-terminated [[transmission line]]s of the bus (i.e. a [[resistor|resistance]] at the end of a transmission line that prev
  7 KB (1,202 words) - 14:32, 28 November 2023
• M7850 parity controller
  ...o error, and by 200 nsec if there is; [[cycle time]] on write is increased by 40 nsec. If an error occurs, an [[Light Emitting Diode|LED]] on the M7850 i ...the associated memory unit(s) are plugged. (Since all the relevant memory modules are hex-sized, the M7850 must go in another slot.) One M7850 can provide pa
  3 KB (434 words) - 00:07, 20 April 2024
• MS750 Memory System
  ...G|300px|thumb|right|/750 backplane from behind, showing the slots occupied by the MS750 in the centre]] * one to eight memory array modules
  3 KB (399 words) - 21:39, 17 May 2024
• VAX-11/750 & VAX-11/751 Revision Control
  | WILL BE NOTED BY AN " ** " IN THE LEFT MARGIN | the kernel and option modules, see sections 5.1 and 6.
  101 KB (10,182 words) - 14:04, 2 July 2022
• VAX-11/785 Revision Control
  DEC Standard 068. changed. This document is under ECO control and will be updated by
  118 KB (7,116 words) - 14:05, 2 July 2022
• Setting Up RIS on ULTRIX V2.0
  * Use at least two computers connected by [[LAN]]. You can either use multiple computers connected by a LAN to solve this, or do a special network setup.
  32 KB (4,724 words) - 22:56, 7 July 2022
• KA730 CPU
  ...m [[PAL]] [[integrated circuit|chips]] extensively, to fit it onto three [[DEC card form factor|hex]] boards: ...to the FPA. The internal memory bus runs from the MCT to the memory array modules.
  2 KB (234 words) - 00:54, 6 July 2022
• Extended Memory Interconnect
  ...ng|thumb|400px|rightt|A four-processor VAX 6200 system built around an XMI bus]] ...000 series]], and also used in other later [[Digital Equipment Corporation|DEC]] [[VAX]] computers, to cope with increased requirements, e.g bandwidth.
  3 KB (491 words) - 01:43, 8 May 2024
• HSC50 Hierarchical Storage Controller
  ...''' and '''HSC50 Mass Storage Server''' in [[Digital Equipment Corporation|DEC]]'s documentation) is an intelligent [[mass storage]] sub-system [[server]] ...is a [[magnetic tape]] formatter, the [[Standard Tape Interconnect]] (STI) bus is used.
  9 KB (1,370 words) - 23:47, 28 December 2023
• VSV11 Graphic System
  ...scanning a large raster array memory in the VSV11, the image is specified by a [[display program]] held in [[main memory]]. The VSV11 used [[Direct Memo ...] was not performed by re-reading the display program; rather, it was done by repetitively scanning the raster memory in the VSV11. The VSV11 was capable
  3 KB (390 words) - 12:39, 27 February 2024
• KDA50 disk controller
  ...ect#SDI Family of DSA Products|SDI disks]] to a [[QBUS]]. It uses a radial bus configuration instead of the conventional daisy-chain (serial) method; thus ...eporting both to the host and through [[Light Emitting Diode|LEDs]] on the modules minimizes repair time.
  6 KB (888 words) - 10:56, 31 August 2023
• Laser System Bus
  ...000 series]], and also used in other later [[Digital Equipment Corporation|DEC]] computers. ...s has special capabilities to support the shared access to memory required by such a system, including support for [[cache coherency]].
  3 KB (396 words) - 01:44, 8 May 2024
• VAX 85x0, 8700, 88xx, and 897x systems
  ...n three different model designations VAX 85xx, VAX 8700, and VAX 8800, the DEC internal superordinate name was "VAX 8800 Family" from the beginning: ...ement a five-stage [[pipeline]]. A high-speed memory interconnect, the NMI bus, links CPUs to memory and the I/O subsystem, which connects to VAXBI buses.
  6 KB (844 words) - 22:15, 29 April 2024
• VAX 8500/8530/8550 Revision Control
  ...| COVERED BY THIS | ...The unit revision control changes in this document will be controlled by the |-----------------|
  233 KB (10,381 words) - 20:20, 22 May 2023
• Installing ULTRIX-11 V1.0 on SIMH
  Wed Dec 31 19:02:20 EST 1969 Wed Dec 31 19:32:43 EST 1969
  33 KB (4,919 words) - 12:31, 21 June 2023
• VAX Diagnostic Supervisor
  ...abbreviated to VAX/DS) is a set of diagnostic software programs for the [[DEC]] [[VAX]] computers and peripheral devices. That's what they must have thought at DEC when they developed their diagnostic software.
  24 KB (3,367 words) - 08:59, 4 April 2024
• Professional 300 Series
  ...PDP-11]]-based [[personal computer]]s from [[Digital Equipment Corporation|DEC]]. ...difference is the use of the [[CTI BUS]] (Computing Terminal Interconnect) bus, which is used solely on the PRO series.
  5 KB (681 words) - 16:37, 5 January 2024
• Talk:ITS machine configurations
  I'm pretty sure that by the time I got to Tech Sq (in 1977), the PDP-6 was no longer in use. It was * Some sort of high-end DEC magtape drive
  25 KB (4,317 words) - 16:47, 17 February 2024
• VAX 8200/8300 Revision Control
  ...| COVERED BY THIS | | BY THE REVISION MATRIX STANDARD EL-00068-00....
  198 KB (5,881 words) - 23:03, 28 March 2024