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• DECnet
  | DAP: Data Access Protocol<BR> ! Data link
  17 KB (2,405 words) - 17:43, 13 January 2024
• QBUS
  ...]] lines (to reduce the pin count), as opposed to the separate address and data lines of the UNIBUS. Another was that although it also supported 4 levels o ...write cycle); and interrupt cycles, in which a device causes the [[Central Processing Unit|CPU]] to perform an interrupt.
  13 KB (2,043 words) - 23:27, 14 January 2024
• UNIBUS
  ...S]], and thus supported several capabilities: the ability of the [[Central Processing Unit|CPU]] to read and write [[main memory]], and device [[register]]s; and The UNIBUS contained 16 data lines, and 18 [[address]] lines, as well as a number of control lines. The
  13 KB (2,162 words) - 23:26, 14 January 2024
• PDP-11/34
  The [[Central Processing Unit|CPU]] came in two variants: the [[KD11-E CPU|KD11-E]] (M7265 and M7266 | 777711 || Source data
  4 KB (536 words) - 19:28, 8 February 2024
• PDP-11/20
  ...duced the [[UNIBUS]] as a universal path to connect together the [[Central Processing Unit|CPU]], [[main memory]] and [[peripheral|devices]]. ...pe puncher/reader. The front panel had lights and switches for address and data (the lights were not LED's).
  6 KB (900 words) - 19:27, 31 December 2023
• PDP-11/24
  ...Kbytes of EUB main memory, using a cross-connection path on the [[Central Processing Unit|CPU]] board. If no KT24 was present, the CPU detected its absence, and ...d devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines. (The lowe
  8 KB (1,395 words) - 23:37, 29 February 2024
• PDP-11/44
  ...relying instead on the UNIBUS, and [[Extended UNIBUS|EUB]]. Its [[Central Processing Unit|CPU]], the [[KD11-Z CPU|KD11-Z]], was the last PDP-11 CPU to be made o ...All devices were attached to a semi-separate UNIBUS (it and the EUB shared data lines, but not [[address]] lines); [[Direct Memory Access|DMA]] devices cou
  4 KB (584 words) - 23:42, 29 February 2024
• PDP-11/45
  ...prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic. ...a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory
  6 KB (895 words) - 23:52, 29 February 2024
• PDP-11/70
  ...IBUS]] [[PDP-11]] system; it basically took the high-performance [[Central Processing Unit|CPU]] of the [[PDP-11/45]] (implemented in [[SSI]] [[Schottky TTL]] lo ...R-xx [[flat cable]]s; two for the [[address]] and control, and two for the data. They run from [[Berg connector]] headers on boards in the KB11 CPU's cache
  5 KB (729 words) - 23:43, 29 February 2024
• PDP-11 architecture
  The [[Central Processing Unit|CPU]] had 8 [[general register|general purpose registers]]; the [[oper ...provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on
  13 KB (1,949 words) - 17:37, 29 February 2024
• VAX-11/780
  {{InfoboxVAX-Data The [[Central Processing Unit|CPU]] was the [[KA780 CPU]]. It could take an optional [[floating poin
  8 KB (1,030 words) - 21:30, 25 April 2024
• VAX-11/782
  {{InfoboxVAX-Data ...ocessor|dual processor]] [[VAX]]; it had two [[KA780 CPU|KA780]] [[Central Processing Unit|CPUs]] connected to up to four [[MA780 Multiport Memory Option|MA780]]
  3 KB (420 words) - 09:14, 15 July 2023
• VAX-11/750
  {{InfoboxVAX-Data ...ne which connected all the major functional units, including the [[Central Processing Unit|CPU]], [[main memory]], and I/O bus adapters, was the [[CPU/Memory Int
  8 KB (1,063 words) - 14:49, 8 May 2024
• PDP-8/E
  ...'PDP-8/F''' was a cost-reduced version of the -8/E with the same [[Central Processing Unit|CPU]], but only a single OMNIBUS [[backplane]]. The '''PDP-8/M''' is t * KD8-E [[OMNIBUS|Data Break]] Interface
  4 KB (618 words) - 14:11, 14 July 2023
• MOS Technology 6502
  ...ntroduced at around $25 it was the least expensive full-featured [[Central Processing Unit|CPU]] on the market by a considerable margin, costing less than one-si ...witch between 16 [[bank switching|banks]] of 64KB memory. The address bus, data bus, and R/W signal are tri-state, unlike the 6502, and the state is contro
  8 KB (1,369 words) - 17:59, 25 June 2021
• VAX-11/730
  {{InfoboxVAX-Data ...way of extensive [[microcoding]] of the large architecture, the [[Central Processing Unit|CPU]] was shrunk to three [[DEC card form factor|hex]] boards. The mac
  5 KB (708 words) - 12:22, 29 March 2023
• Timeline of Norsk Data
  * In July, Norsk Data-Elektronikk is founded. * The company changes name from "NORDATA Norsk Data-Elektronikk" to "Norsk Data A/S"
  7 KB (950 words) - 12:59, 23 August 2016
• NORD-10
  | manufacturer = [[Norsk Data]] ...plications and for [[real-time]] multiprogram systems, produced by [[Norsk Data]]. It was introduced in 1973. The later follow up model, NORD-10/S, introdu
  8 KB (1,313 words) - 13:52, 11 July 2023
• MicroVAX I
  {{InfoboxVAX-Data ...n|DEC]]. It used the [[QBUS]] as its primary [[bus]] between the [[Central Processing Unit|CPU]] (the [[KD32 CPU]]) and [[main memory]], the only [[VAX]] to do s
  10 KB (1,543 words) - 02:27, 7 May 2024
• MicroVAX II
  {{InfoboxVAX-Data ...II''' was a small [[VAX]], with the [[KA630 CPU‎‎]] for its [[Central Processing Unit|CPU]]. Its [[bus]] between the CPU and [[main memory]] was a special b
  5 KB (716 words) - 13:37, 6 May 2024
• PDP-10
  ...the KS10 were available in [[multi-processor]] versions with two [[Central Processing Unit|CPUs]]. ...ided for the latter; it allowed peripherals to [[interrupt]] the [[Central Processing Unit|CPU]], and supported [[programmed I/O]] (including block transfers).
  11 KB (1,640 words) - 20:59, 8 March 2024
• PDP-8 architecture
  ...in one field could access data in the same field by direct addressing, or data in another field with indirect addressing. ...ory controller. The 62X1 instuction (CDF, Change Data Field) would set the data field to X. Similarly 62X2, CIF, set the instruction field, 62X3 set both.
  22 KB (3,497 words) - 19:34, 29 November 2022
• Bus
  In computer [[architecture]], a '''bus''' is a subsystem that transfers data or power between computer components inside a computer or between computers ..., it might take too long for the program to check again, resulting in lost data. Engineers thus arranged for the peripherals to interrupt the CPU. The in
  14 KB (2,170 words) - 05:09, 5 September 2019
• VAX-11/785
  {{InfoboxVAX-Data ...1/785''' was an upgraded version of the [[VAX-11/780|/780]]; its [[Central Processing Unit|CPUs]] used [[Advanced Schottky]] [[logic]]. A /780 could be upgraded
  2 KB (193 words) - 04:26, 13 January 2024
• LEO
  * [http://www.cs.man.ac.uk/CCS/res/res02.htm#d Designing a computer for data processing] - personal memories from John Pinkerton, the principal engineer
  2 KB (262 words) - 19:03, 18 March 2024
• MicroVAX 3800/3900
  {{InfoboxVAX-Data ...kplane. (The [[address space]] of the [[QBUS]] was limited to 4MB, and the data section is only 16 bits wide.)
  3 KB (380 words) - 07:06, 31 January 2024
• History of Zork
  ...programming languages like MDL (an important influence on modern Lisp) to data bases, electronic mail and artificially intelligent systems -- if only cent ...ms for keeping track of documents, handling electronic correspondence, and processing text. When Zork was added to the list of possibilities, Joel and Marc worke
  38 KB (6,681 words) - 16:32, 19 December 2018
• Incompatible Timesharing System
  ...al memory|paging]] [[hardware]] (which that generation of PDP-10 [[Central Processing Unit|CPU]] did not have). It later ran on the [[KL10]] and [[KS10]] models ...n units of either [[character]]s or [[word]]s (although an entire block of data could be transferred by a single [[system call]], if desired). All the usua
  12 KB (1,926 words) - 21:29, 8 February 2024
• ITS DDT Guide
  command. It is so powerful that it can leave DDT's data bases ("kills") the current job. All the data in it is lost. The $J
  171 KB (29,660 words) - 17:55, 28 December 2018
• Top
  immediately read for processing. See the section on the process (text, data, and stack), RES is the current
  11 KB (1,552 words) - 13:03, 24 April 2024
• TROPIX Manual
  processing of devices already supported. ........ (and other data from computer) ............
  91 KB (12,020 words) - 17:55, 13 August 2019
• Operating system
  ...mple, operating systems provided [[file system]]s for users to store their data in. ...r could not interfere with another user, so protection of users (and their data, stored on disk) from each other became another function of the operating s
  4 KB (608 words) - 15:04, 9 September 2022
• VT100
  ...the VT100 into [[VT52]] mode (one of the VT series' features) because VT52 processing had less overhead.[1] ...and use every other measure to improve how fast the terminal could process data (see above).
  4 KB (664 words) - 14:34, 11 August 2023
• Intel 80386
  ...r '''i386''' for short) is the 4th generation [[microprocessor]] [[Central Processing Unit|CPU]] from [[Intel]] based on the 8088/8086 CPU. The 386 was a 32-bit ...could only address 16MB of RAM maximum. The 386SX also only could transfer data 16 bits at a time, so reading a 32-bit word took two reads. This basically
  2 KB (372 words) - 01:23, 30 December 2021
• J-11 chip set
  ...ls. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier. ...full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains bu
  2 KB (242 words) - 23:19, 29 February 2024
• Intel 4004
  ...-only memory|ROM]], [[Random Access Memory|RAM]] was only used for storing data, and this complicated the life of the [[programmer]] somewhat. ...by the Wxx instructions. (Also, the CM-RAM[0123] lines from the [[Central Processing Unit|processor]] chip are used to control "4002 RAM chips".)
  5 KB (796 words) - 16:01, 14 July 2023
• IBM AT
  ...y Standard Architecture|ISA]] slots, and the 'advanced' [[i286]] [[Central Processing Unit|CPU]]. The IBM AT unlike the [[IBM XT]] is fully 16 bit, with a 16-bit [[data bus]], 24-bit [[address bus]], and 16-bit ISA expansion bus. IBM had also
  2 KB (396 words) - 00:41, 20 October 2018
• COBOL
  ...arily found in [[mainframe]] environments, and is used in business [[batch processing]]. * data
  3 KB (392 words) - 18:34, 14 January 2024
• MSV11-J memory module
  ...-JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit|CPU]], such as the [[KDJ11-B CPU|KDJ11-B]]. In systems such as the [[P The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[w
  8 KB (1,374 words) - 00:43, 30 July 2023
• KA630 CPU
  {{InfoboxVAXCPU-Data The '''KA630''' is the [[Central Processing Unit|CPU]] used in [[Digital Equipment Corporation|DEC]]'s [[MicroVAX II]].
  2 KB (174 words) - 06:15, 28 June 2022
• Starlink
  ...anticipated flood of data in digital form which would be generated by new data acquisition techniques. In April 1978, SRC set up a Panel on Astronomical Image and Data Processing under the chairmanship of Professor Mike Disney to ascertain the computing
  1 KB (194 words) - 01:54, 20 December 2018
• Intel 8086
  ...16-bit CPU, which means the internal [[data bus]], along with the external data bus. ...hile it retained the same addressing modes, and instructions, the external data bus was 8 bits wide. The 8088 was the primary CPU found in the [[IBM 5150|
  1 KB (210 words) - 13:29, 3 November 2018
• Intel 80186
  ...tral Processing Unit|CPU]]. It also exists in an 80188 variant (with 8-bit data bus, like the [[Intel 8088]]).
  975 bytes (146 words) - 13:32, 3 November 2018
• Real Programmers Don't Use Pascal
  Real Programmers do List Processing in FORTRAN. ...ming language with all sorts of complications. The worst thing about fancy data types is that you have to declare them, and Real Programming Languages, as
  22 KB (3,770 words) - 14:23, 25 August 2021
• Linux 0.00
  # The third is the system of data # Register all of the data, all point system, gdt Table 3
  14 KB (1,991 words) - 01:23, 20 December 2018
• DZ11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line, using [[interrupt]]s. A 64-entry |Transmit Data Register || TDR || 760106
  5 KB (730 words) - 02:26, 19 February 2023
• Installing NetBSD 5.0.2 on the SIMH MicroVAX II
  # Based on the maketape.c program and the maketape.data data file. i: Text Processing Tools No
  8 KB (1,125 words) - 02:02, 18 November 2010
• NetBSD 0.9 announcement
  add delay loop to lpa and lpt drivers to allow data port fixed bug in ECHONL processing (andrew)
  29 KB (4,794 words) - 18:15, 16 December 2018
• DLV11-E asynchronous serial line interface
  ...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser
  3 KB (489 words) - 01:18, 17 February 2023
• DLV11-J asynchronous serial line interface
  ...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h That line can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser
  4 KB (684 words) - 01:20, 17 February 2023

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