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  • 2.6.3 PDP-11 compatibility................. 18 2.9BSD has vfork for the PDP-11. 4.3BSD will eliminate
    113 KB (13,419 words) - 02:06, 17 December 2018
  • The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[Emitter-coupled logic|ECL]], on [[DEC card form fact ...]]s; they allowed connection of a [[PDP-11]] [[front end]]. At least one PDP-11, the 'master', was ''required''; it could [[bootstrap]] the KL10, including
    11 KB (1,737 words) - 13:06, 2 April 2024
  • ...''KA10''' was the first generation of [[PDP-10]] [[Central Processing Unit|processors]] (themselves, exact re-implementations of the earlier [[PDP-6]] architectu [[Category: PDP-10 Processors]]
    2 KB (298 words) - 07:28, 6 September 2023
  • The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture [[Category: PDP-10 Processors]]
    3 KB (382 words) - 13:23, 5 November 2023
  • [[Image:KY11-LB.jpg|thumb|right|300px|A KY11-LB Programmer's Console on a PDP-11/04]] ...1-LB Programmer's Console''' was an option for the [[PDP-11/04]] and the [[PDP-11/34]] (the units for the two machines differed only in the number painted on
    7 KB (1,114 words) - 20:56, 24 October 2022
  • ...the progenitor of the semi-standard [[FP11 floating point]] used in many [[PDP-11]]s. [[Category: PDP-11 UNIBUS Processors]]
    1 KB (201 words) - 02:17, 13 October 2022
  • ...ogenitor of the semi-standard [[FP11 floating point]] used in many later [[PDP-11]]s. [[Category: PDP-11 UNIBUS Processors]]
    1 KB (209 words) - 02:18, 13 October 2022
  • ...rd form factor|quad-height]] board, and is used in the [[PDP-11/83]] and [[PDP-11/84]] systems. ...rts the [[KTJ11-B UNIBUS adapter]], a QBUS->[[UNIBUS]] adapter used in the PDP-11/84.
    2 KB (391 words) - 16:40, 6 February 2024
  • ...rd form factor|quad-height]] board, and is used in the [[PDP-11/93]] and [[PDP-11/94]] systems. [[Category: PDP-11 QBUS Processors]]
    2 KB (254 words) - 16:41, 6 February 2024
  • ...apability to systems built around those CPU cards, the [[PDP-11/84]] and [[PDP-11/94]] systems respectively. ...ed as regular Q22/CD QBUS slots, by removing two jumpers. EK-PDP84-TM-PR4 (PDP-11/84 Technical Manual) says (in section 2.1.14, "Backplane (H9277-A)", pg. 2-
    6 KB (1,060 words) - 16:35, 6 February 2024
  • ...ing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP-11 CPU which was not [[microcode]]d (since the cheap [[read-only memory|ROMs]] ...a 16x16 [[register file]], of which half are used to hold the machine's [[PDP-11 architecture|general registers]]; two of the others are used for internal t
    9 KB (1,356 words) - 23:10, 29 February 2024
  • The '''KDF11 CPUs''' are single-[[printed circuit board|board]] [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Fonz' [[F-11 chip set ...] - M8186 - [[QBUS]] [[DEC card form factor|dual]]-width CPU used in the [[PDP-11/23]]
    3 KB (394 words) - 13:49, 29 March 2022
  • ...e other [[KDF11 CPUs]]. It plugs into a custom slot in the likewise custom PDP-11/24 [[backplane]] ([[DEC part number]] 54-13817, assembly 70-16905). ...ouble-width [[KEF11-B CIS chip|KEF11-B]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In a
    6 KB (1,087 words) - 16:16, 6 February 2024
  • There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset] ...M8190 - QBUS quad-width CPU used in the [[PDP-11/73]], [[PDP-11/83]] and [[PDP-11/84]]
    3 KB (457 words) - 14:32, 21 February 2023
  • ...ed 'Fonz') was [[DEC]]'s second [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Proce ...e optional [[KTF11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which
    2 KB (384 words) - 23:50, 28 March 2022
  • [[Category: PDP-11 Processors]]
    181 bytes (30 words) - 16:09, 16 December 2018
  • ...point chip''' is an optional [[integrated circuit|chip]] for [[KDF11 CPUs|PDP-11 CPUs]] which use the [[F-11 chip set]]. It contains [[microcode]] to implem [[Category: PDP-11 Processors]]
    899 bytes (153 words) - 17:43, 12 March 2021
  • .... It implemented the standard [[PDP-11 Memory Management]] (but only the [[PDP-11 Memory Management#Simplified subset|simplified subset]]). [[Category: PDP-11 Processors]]
    762 bytes (124 words) - 13:41, 12 August 2022
  • ...nt]] unit for the [[KD11-A CPU]] of the [[PDP-11/40]]. It implements the [[PDP-11]] [[FIS floating point]], not the full [[FP11 floating point]]. [[Category: PDP-11 UNIBUS Processors]]
    2 KB (246 words) - 02:34, 12 October 2022
  • ...1-E CPU''' was the first [[Central Processing Unit|CPU]] version for the [[PDP-11/34]]; it consisted of two [[DEC card form factor|hex]] [[printed circuit bo ...t|floating point]] unit or the [[KK11-A Cache Memory|KK11-A]] [[cache]]; a PDP-11/34 system needed the upgraded [[KD11-EA CPU]] for that.
    5 KB (791 words) - 02:23, 6 December 2022
  • ...he [[Central Processing Unit|CPU]] for the [[PDP-11/34A]] version of the [[PDP-11/34]]; it consisted of two [[DEC card form factor|hex]] [[printed circuit bo | E74 || 23-110A1 || 32x8 || [[PDP-11 Extended Instruction Set|EIS]] Decoder
    6 KB (1,045 words) - 22:47, 31 March 2022
  • [[Image:KY11-LA.jpg|thumb|right|300px|A KY11-LA Operator's Console on a PDP-11/04]] ...''' was the standard basic [[front panel]] for the [[PDP-11/04]] and the [[PDP-11/34]] (the units for the two machines differed only in the number painted on
    2 KB (358 words) - 18:29, 3 April 2022
  • ...[[floating point]] [[co-processor]] for the DCJ11 [[J-11 chip set|J-11]] [[PDP-11]] [[Central Processing Unit|CPU]] [[integrated circuit|chip]], which implem * [https://www.subgeniuskitty.com/development/pdp-11/references/fpj11_compat DCJ11/FPJ11 Compatibility]
    2 KB (276 words) - 21:06, 2 July 2023
  • The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture [[Category: PDP-10 Processors]]
    8 KB (1,237 words) - 19:48, 14 July 2023
  • ...[DEC card form factor|hex]] board, the '''M8267'''. It supports the full [[PDP-11]] [[FP11 floating point]]. ..., and a 10 pin connector to the M8266 card. (This was likely because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support t
    4 KB (734 words) - 02:17, 13 October 2022
  • ...U through an '[[over the back]]' connector. (This was likely because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support t ...s are at the same locations as some of the memory/cache registers in the [[PDP-11/70]], but they are generally incompatible with those in the /70, except as
    4 KB (553 words) - 02:36, 12 October 2022
  • ...''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/35]] and [[PDP-11/40]] was a multi-board [[microcode|micro-programmed]] processor. Support for the [[PDP-11 Extended Instruction Set|EIS]] was optional, with the [[KE11-E Extended Ins
    4 KB (588 words) - 05:52, 8 April 2024
  • ...the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings). ...also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connect
    5 KB (664 words) - 17:27, 7 November 2023
  • ...[graphics terminal]]s, and provide [[Chaosnet]] [[front end]]s to [[KL10]] processors. [[Category: PDP-11 Operating Systems]]
    3 KB (347 words) - 08:50, 27 February 2024
  • ...''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/05]] and [[PDP-11/10]] was a two-board [[microcode|micro-programmed]] processor contained on ...-cost PDP-11s, it did not support either hardware [[floating point]], or [[PDP-11 Extended Instruction Set|EIS]]. It did include an [[asynchronous serial lin
    11 KB (1,726 words) - 21:07, 2 July 2023
  • 1 KB (166 words) - 00:32, 23 June 2020
  • ...-B Floating-Point Processor]] and [[KT11-C Memory Management Unit]] of the PDP-11/45 plugged into the CPU's [[backplane]]. ...e special high-speed [[MS11 Semiconductor Memory System]], specific to the PDP-11/45, which plugged into a special [[bus]], the Fastbus, which was also part
    3 KB (395 words) - 21:08, 2 July 2023
  • ...ocessing Unit|CPU]] is the later [[Central Processing Unit|CPU]] for the [[PDP-11/45]]; it differed from the earlier [[KB11-A CPU]] in that is used the [[syn ...e special high-speed [[MS11 Semiconductor Memory System]], specific to the PDP-11/45, which plugged into a special [[bus]], the Fastbus, which was also part
    2 KB (307 words) - 12:32, 11 October 2022
  • ...Memory Management]] architecture; in fact, the KT11-C is the archetype for PDP-11 memory management units. [[Category: PDP-11 UNIBUS Processors]]
    2 KB (231 words) - 02:38, 12 October 2022
  • ...tional [[PDP-11 Extended Instruction Set]] for the [[KD11-A CPU]] of the [[PDP-11/40]]; it implements multiply, divide, and multi-bit shift instructions. It [[Category: PDP-11 UNIBUS Processors]]
    2 KB (304 words) - 02:33, 12 October 2022
  • ...the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a sing [[Category: PDP-11 UNIBUS Processors]]
    961 bytes (149 words) - 02:20, 13 October 2022
  • ...the terminal letter code 'Z' was a tip to the fact that it was the last [[PDP-11]] CPU to be made out of discrete [[integrated circuit|chips]], and not a [[ Full [[PDP-11 Memory Management]] and a [[cache]] (the [[KK11-B Cache Memory|KK11-B]]) we
    4 KB (668 words) - 15:59, 6 February 2024
  • ...U]] is the earlier CPU for the [[PDP-11/70]]. It is heavily based on the [[PDP-11/45]]'s [[KB11-A CPU]]; the -11/70 is basically an -11/45 with a [[cache]], Full [[PDP-11 Memory Management]] and the cache were standard on all KB11-B's. It used a
    3 KB (456 words) - 21:08, 2 July 2023
  • The '''KB11-C''' [[Central Processing Unit|CPU]] is the later CPU for the [[PDP-11/70]]; it is basically the same as the earlier [[KB11-B CPU]], except that i '''''Note''''': ''The DEC documentation contains an error here. The "PDP-11/70 Maintenance and Installation Manual", EK-11070-MM-002, refers to the M81
    2 KB (260 words) - 21:03, 24 October 2022
  • ...oating point]] units of many [[PDP-11]]s); [[channel]]s are effectively co-processors which are specialized to doing [[input/output|I/O]].
    528 bytes (79 words) - 16:25, 15 December 2018
  • ...ircuit board|boards]] which use the [[F-11 chip set]]; it implements the [[PDP-11 Commercial Instruction Set]]. [[Category: PDP-11 Processors]]
    650 bytes (102 words) - 18:57, 30 May 2021
  • [[Category: PDP-11 Processors]]
    2 KB (383 words) - 02:31, 12 October 2022
  • ...[[PDP-11]]s. (No [[PDP-8 family|PDP-8]] or other [[List of Programmed Data Processors|early DEC system]] [[device controller]] has yet been seen for it, although
    2 KB (258 words) - 22:12, 14 August 2023
  • ...it|chip]] for [[LSI-11 chip set]] which adds support for a subset of the [[PDP-11 Commercial Instruction Set]], sometimes known as DIS ([[DIBOL]] instruction It also apparently includes the [[PDP-11 Extended Instruction Set]] (but not the [[FIS floating point|FIS]]).
    1 KB (241 words) - 21:11, 2 July 2023
  • ...grated circuit|chip]] for [[LSI-11 chip set]] which adds support for the [[PDP-11 Extended Instruction Set]], but not also [[FIS floating point]] (like the [ [[Category: PDP-11 Processors]]
    466 bytes (75 words) - 21:12, 2 July 2023
  • ...n any of the three uROM positions. The first two uROMs contain the basic [[PDP-11]] [[instruction set]]; the third uROM is optional, and a number of differen ...Commercial Instruction Set‎|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but
    5 KB (773 words) - 22:42, 20 December 2023
  • ...rd form factor|hex]] [[printed circuit board|card]] (the M7263), the first PDP-11 CPU to be built on a single card. ...ction Set|EIS]] [[instruction]]s, or the various instructions added to the PDP-11 [[instruction set]] (XOR, SOB, SXT and MARK).
    2 KB (385 words) - 22:37, 31 March 2022
  • ...1/40]] which provided [[memory management]]. It did not provide the full [[PDP-11 Memory Management]], but the simplified subset; in fact, the KT11-D is the ...ee e.g. EK-11040-TM-002, pg. 4-22) but this may just be an artifact of DEC PDP-11 software.
    2 KB (258 words) - 00:29, 30 December 2023
  • ...]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access ( * [http://www.bitsavers.org/pdf/dec/pdp11/1160/ PDP-11/60] - BitSavers
    4 KB (536 words) - 12:34, 11 October 2022
  • ...ional [[hardware]] [[floating point]] unit for the [[KD11-K CPU]] of the [[PDP-11/60]]. The KD11-K provided the full [[FP11 floating point]] using [[microcod [[Category: PDP-11 UNIBUS Processors]]
    1 KB (229 words) - 02:19, 13 October 2022

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