F-11 chip set
The main CPU was implemented in two chips (carried on a single DIP carrier): the data paths chip (DC302, DEC part # 21-15541-Ax, where x is a capital letter giving the revision; B is the most common, although C has been seen), which contains the registers, ALU, etc; and the control chip (DC303, DEC part # 23-001C7-Ax, although only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic.
Unlike the first microprocessor implementation (the LSI-11), the F-11 chip set implemented the full PDP-11 architecture, including the optional KTF11-A memory management chip which implemented standard PDP-11 Memory Management, and the optional KEF11-A floating point chip which implemented the FP11-compatible floating point.
(The KEF11-A requires the KTF11-A, since the floating point registers are actually in the KTF11-A; probably because the KEF11-A is microcode, and there aren't enough pins for both the data bus, and the microcode bus.)
The F-11 chip set includes microcode which provides 'front panel' functionality named 'ODT'; the ability to read and write to memory, start the process, etc. However, the original version of the KDF11-A only supported 18-bit addressing, and even though later versions supported 22-bit addressing, ODT in the KDF11's was always limited to 18-bit addressing: i.e. it is impossible to interact with memory above 256 Kbytes from ODT.
The later KDJ11 CPUs do not have this limitation.