F-11 chip set
The F-11 chip set (code-named 'Fonz') was DEC's second microprocessor implementation of the PDP-11 architecture. It was used in the KDF11 CPUs. The main CPU was implemented in two chips (carried on a single DIP carrier).
Unlike the first microprocessor implementation (the LSI-11), the full F-11 chip set implemented the full PDP-11 architecture, including the optional KTF11-A memory management chip which implemented standard PDP-11 Memory Management, and the optional KEF11-A floating point chip which implemented the FP11-compatible floating point.
(The KEF11-A requires the KTF11-A, since the floating point registers are actually in the KTF11-A. The reason why is not known; although the KEF11-A is microcode, there are enough pins for both the data bus, and the microcode bus.)
The data paths chip is the DC302, DEC part number 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, ALU, etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).
The F-11 chip set includes microcode which provides 'front panel' functionality named 'ODT'; the ability to read and write to main memory, start the processor, etc. However, the original version of the KDF11-A only supported 18-bit addressing, and even though later versions supported 22-bit addressing, ODT in the KDF11's was always limited to 18-bit addressing: i.e. it is impossible to interact with memory above 256 Kbytes from ODT.
The later KDJ11 CPUs do not have this limitation.
|v • d • e PDP-11 Computers and Peripherals|
|UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 • PDP-11/05 • PDP-11/10 • PDP-11/34 • PDP-11/04 • PDP-11/44 • PDP-11/60 • PDP-11/24 • PDP-11/84 • PDP-11/94|