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• DECnet
  | DAP: Data Access Protocol<BR> ! Data link
  17 KB (2,405 words) - 17:43, 13 January 2024
• QBUS
  ...]] lines (to reduce the pin count), as opposed to the separate address and data lines of the UNIBUS. Another was that although it also supported 4 levels o ...write cycle); and interrupt cycles, in which a device causes the [[Central Processing Unit|CPU]] to perform an interrupt.
  13 KB (2,043 words) - 23:27, 14 January 2024
• UNIBUS
  ...S]], and thus supported several capabilities: the ability of the [[Central Processing Unit|CPU]] to read and write [[main memory]], and device [[register]]s; and The UNIBUS contained 16 data lines, and 18 [[address]] lines, as well as a number of control lines. The
  13 KB (2,162 words) - 23:26, 14 January 2024
• PDP-11/34
  The [[Central Processing Unit|CPU]] came in two variants: the [[KD11-E CPU|KD11-E]] (M7265 and M7266 | 777711 || Source data
  4 KB (536 words) - 19:28, 8 February 2024
• PDP-11/20
  ...duced the [[UNIBUS]] as a universal path to connect together the [[Central Processing Unit|CPU]], [[main memory]] and [[peripheral|devices]]. ...pe puncher/reader. The front panel had lights and switches for address and data (the lights were not LED's).
  6 KB (900 words) - 19:27, 31 December 2023
• PDP-11/24
  ...Kbytes of EUB main memory, using a cross-connection path on the [[Central Processing Unit|CPU]] board. If no KT24 was present, the CPU detected its absence, and ...d devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines. (The lowe
  8 KB (1,395 words) - 23:37, 29 February 2024
• PDP-11/44
  ...relying instead on the UNIBUS, and [[Extended UNIBUS|EUB]]. Its [[Central Processing Unit|CPU]], the [[KD11-Z CPU|KD11-Z]], was the last PDP-11 CPU to be made o ...All devices were attached to a semi-separate UNIBUS (it and the EUB shared data lines, but not [[address]] lines); [[Direct Memory Access|DMA]] devices cou
  4 KB (584 words) - 23:42, 29 February 2024
• PDP-11/45
  ...prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic. ...a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory
  6 KB (895 words) - 23:52, 29 February 2024
• PDP-11/70
  ...IBUS]] [[PDP-11]] system; it basically took the high-performance [[Central Processing Unit|CPU]] of the [[PDP-11/45]] (implemented in [[SSI]] [[Schottky TTL]] lo ...R-xx [[flat cable]]s; two for the [[address]] and control, and two for the data. They run from [[Berg connector]] headers on boards in the KB11 CPU's cache
  5 KB (729 words) - 23:43, 29 February 2024
• PDP-11 architecture
  The [[Central Processing Unit|CPU]] had 8 [[general register|general purpose registers]]; the [[oper ...provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on
  13 KB (1,949 words) - 17:37, 29 February 2024
• VAX-11/780
  {{InfoboxVAX-Data The [[Central Processing Unit|CPU]] was the [[KA780 CPU]]. It could take an optional [[floating poin
  8 KB (1,030 words) - 21:30, 25 April 2024
• VAX-11/782
  {{InfoboxVAX-Data ...ocessor|dual processor]] [[VAX]]; it had two [[KA780 CPU|KA780]] [[Central Processing Unit|CPUs]] connected to up to four [[MA780 Multiport Memory Option|MA780]]
  3 KB (420 words) - 09:14, 15 July 2023
• VAX-11/750
  {{InfoboxVAX-Data ...ne which connected all the major functional units, including the [[Central Processing Unit|CPU]], [[main memory]], and I/O bus adapters, was the [[CPU/Memory Int
  8 KB (1,063 words) - 14:49, 8 May 2024
• PDP-8/E
  ...'PDP-8/F''' was a cost-reduced version of the -8/E with the same [[Central Processing Unit|CPU]], but only a single OMNIBUS [[backplane]]. The '''PDP-8/M''' is t * KD8-E [[OMNIBUS|Data Break]] Interface
  4 KB (618 words) - 14:11, 14 July 2023
• MOS Technology 6502
  ...ntroduced at around $25 it was the least expensive full-featured [[Central Processing Unit|CPU]] on the market by a considerable margin, costing less than one-si ...witch between 16 [[bank switching|banks]] of 64KB memory. The address bus, data bus, and R/W signal are tri-state, unlike the 6502, and the state is contro
  8 KB (1,369 words) - 17:59, 25 June 2021
• VAX-11/730
  {{InfoboxVAX-Data ...way of extensive [[microcoding]] of the large architecture, the [[Central Processing Unit|CPU]] was shrunk to three [[DEC card form factor|hex]] boards. The mac
  5 KB (708 words) - 12:22, 29 March 2023
• Timeline of Norsk Data
  * In July, Norsk Data-Elektronikk is founded. * The company changes name from "NORDATA Norsk Data-Elektronikk" to "Norsk Data A/S"
  7 KB (950 words) - 12:59, 23 August 2016
• NORD-10
  | manufacturer = [[Norsk Data]] ...plications and for [[real-time]] multiprogram systems, produced by [[Norsk Data]]. It was introduced in 1973. The later follow up model, NORD-10/S, introdu
  8 KB (1,313 words) - 13:52, 11 July 2023
• MicroVAX I
  {{InfoboxVAX-Data ...n|DEC]]. It used the [[QBUS]] as its primary [[bus]] between the [[Central Processing Unit|CPU]] (the [[KD32 CPU]]) and [[main memory]], the only [[VAX]] to do s
  10 KB (1,543 words) - 02:27, 7 May 2024
• MicroVAX II
  {{InfoboxVAX-Data ...II''' was a small [[VAX]], with the [[KA630 CPU‎‎]] for its [[Central Processing Unit|CPU]]. Its [[bus]] between the CPU and [[main memory]] was a special b
  5 KB (716 words) - 13:37, 6 May 2024
• PDP-10
  ...the KS10 were available in [[multi-processor]] versions with two [[Central Processing Unit|CPUs]]. ...ided for the latter; it allowed peripherals to [[interrupt]] the [[Central Processing Unit|CPU]], and supported [[programmed I/O]] (including block transfers).
  11 KB (1,640 words) - 20:59, 8 March 2024
• PDP-8 architecture
  ...in one field could access data in the same field by direct addressing, or data in another field with indirect addressing. ...ory controller. The 62X1 instuction (CDF, Change Data Field) would set the data field to X. Similarly 62X2, CIF, set the instruction field, 62X3 set both.
  22 KB (3,497 words) - 19:34, 29 November 2022
• Bus
  In computer [[architecture]], a '''bus''' is a subsystem that transfers data or power between computer components inside a computer or between computers ..., it might take too long for the program to check again, resulting in lost data. Engineers thus arranged for the peripherals to interrupt the CPU. The in
  14 KB (2,170 words) - 05:09, 5 September 2019
• VAX-11/785
  {{InfoboxVAX-Data ...1/785''' was an upgraded version of the [[VAX-11/780|/780]]; its [[Central Processing Unit|CPUs]] used [[Advanced Schottky]] [[logic]]. A /780 could be upgraded
  2 KB (193 words) - 04:26, 13 January 2024
• LEO
  * [http://www.cs.man.ac.uk/CCS/res/res02.htm#d Designing a computer for data processing] - personal memories from John Pinkerton, the principal engineer
  2 KB (262 words) - 19:03, 18 March 2024
• MicroVAX 3800/3900
  {{InfoboxVAX-Data ...kplane. (The [[address space]] of the [[QBUS]] was limited to 4MB, and the data section is only 16 bits wide.)
  3 KB (380 words) - 07:06, 31 January 2024
• History of Zork
  ...programming languages like MDL (an important influence on modern Lisp) to data bases, electronic mail and artificially intelligent systems -- if only cent ...ms for keeping track of documents, handling electronic correspondence, and processing text. When Zork was added to the list of possibilities, Joel and Marc worke
  38 KB (6,681 words) - 16:32, 19 December 2018
• Incompatible Timesharing System
  ...al memory|paging]] [[hardware]] (which that generation of PDP-10 [[Central Processing Unit|CPU]] did not have). It later ran on the [[KL10]] and [[KS10]] models ...n units of either [[character]]s or [[word]]s (although an entire block of data could be transferred by a single [[system call]], if desired). All the usua
  12 KB (1,926 words) - 21:29, 8 February 2024
• ITS DDT Guide
  command. It is so powerful that it can leave DDT's data bases ("kills") the current job. All the data in it is lost. The $J
  171 KB (29,660 words) - 17:55, 28 December 2018
• Top
  immediately read for processing. See the section on the process (text, data, and stack), RES is the current
  11 KB (1,552 words) - 13:03, 24 April 2024
• TROPIX Manual
  processing of devices already supported. ........ (and other data from computer) ............
  91 KB (12,020 words) - 17:55, 13 August 2019
• Operating system
  ...mple, operating systems provided [[file system]]s for users to store their data in. ...r could not interfere with another user, so protection of users (and their data, stored on disk) from each other became another function of the operating s
  4 KB (608 words) - 15:04, 9 September 2022
• VT100
  ...the VT100 into [[VT52]] mode (one of the VT series' features) because VT52 processing had less overhead.[1] ...and use every other measure to improve how fast the terminal could process data (see above).
  4 KB (664 words) - 14:34, 11 August 2023
• Intel 80386
  ...r '''i386''' for short) is the 4th generation [[microprocessor]] [[Central Processing Unit|CPU]] from [[Intel]] based on the 8088/8086 CPU. The 386 was a 32-bit ...could only address 16MB of RAM maximum. The 386SX also only could transfer data 16 bits at a time, so reading a 32-bit word took two reads. This basically
  2 KB (372 words) - 01:23, 30 December 2021
• J-11 chip set
  ...ls. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier. ...full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains bu
  2 KB (242 words) - 23:19, 29 February 2024
• Intel 4004
  ...-only memory|ROM]], [[Random Access Memory|RAM]] was only used for storing data, and this complicated the life of the [[programmer]] somewhat. ...by the Wxx instructions. (Also, the CM-RAM[0123] lines from the [[Central Processing Unit|processor]] chip are used to control "4002 RAM chips".)
  5 KB (796 words) - 16:01, 14 July 2023
• IBM AT
  ...y Standard Architecture|ISA]] slots, and the 'advanced' [[i286]] [[Central Processing Unit|CPU]]. The IBM AT unlike the [[IBM XT]] is fully 16 bit, with a 16-bit [[data bus]], 24-bit [[address bus]], and 16-bit ISA expansion bus. IBM had also
  2 KB (396 words) - 00:41, 20 October 2018
• COBOL
  ...arily found in [[mainframe]] environments, and is used in business [[batch processing]]. * data
  3 KB (392 words) - 18:34, 14 January 2024
• MSV11-J memory module
  ...-JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit|CPU]], such as the [[KDJ11-B CPU|KDJ11-B]]. In systems such as the [[P The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[w
  8 KB (1,374 words) - 00:43, 30 July 2023
• KA630 CPU
  {{InfoboxVAXCPU-Data The '''KA630''' is the [[Central Processing Unit|CPU]] used in [[Digital Equipment Corporation|DEC]]'s [[MicroVAX II]].
  2 KB (174 words) - 06:15, 28 June 2022
• Starlink
  ...anticipated flood of data in digital form which would be generated by new data acquisition techniques. In April 1978, SRC set up a Panel on Astronomical Image and Data Processing under the chairmanship of Professor Mike Disney to ascertain the computing
  1 KB (194 words) - 01:54, 20 December 2018
• Intel 8086
  ...16-bit CPU, which means the internal [[data bus]], along with the external data bus. ...hile it retained the same addressing modes, and instructions, the external data bus was 8 bits wide. The 8088 was the primary CPU found in the [[IBM 5150|
  1 KB (210 words) - 13:29, 3 November 2018
• Intel 80186
  ...tral Processing Unit|CPU]]. It also exists in an 80188 variant (with 8-bit data bus, like the [[Intel 8088]]).
  975 bytes (146 words) - 13:32, 3 November 2018
• Real Programmers Don't Use Pascal
  Real Programmers do List Processing in FORTRAN. ...ming language with all sorts of complications. The worst thing about fancy data types is that you have to declare them, and Real Programming Languages, as
  22 KB (3,770 words) - 14:23, 25 August 2021
• Linux 0.00
  # The third is the system of data # Register all of the data, all point system, gdt Table 3
  14 KB (1,991 words) - 01:23, 20 December 2018
• DZ11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line, using [[interrupt]]s. A 64-entry |Transmit Data Register || TDR || 760106
  5 KB (730 words) - 02:26, 19 February 2023
• Installing NetBSD 5.0.2 on the SIMH MicroVAX II
  # Based on the maketape.c program and the maketape.data data file. i: Text Processing Tools No
  8 KB (1,125 words) - 02:02, 18 November 2010
• NetBSD 0.9 announcement
  add delay loop to lpa and lpt drivers to allow data port fixed bug in ECHONL processing (andrew)
  29 KB (4,794 words) - 18:15, 16 December 2018
• DLV11-E asynchronous serial line interface
  ...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser
  3 KB (489 words) - 01:18, 17 February 2023
• DLV11-J asynchronous serial line interface
  ...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h That line can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser
  4 KB (684 words) - 01:20, 17 February 2023
• DLV11 asynchronous serial line interface
  ...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen.
  2 KB (378 words) - 19:15, 7 July 2023
• TPA-11/580
  ...open architecture member of the KFKI TPA-family. With a microcoded central processing unit, the speed and performance is due to its efficient instruction set and ...lates the 30-bit SBI addresses to 18-bit UNIBUS addresses, handles DMA and data buffering (The UBA does 4 UNIBUS-cycles on one SBI cycle).
  4 KB (587 words) - 00:38, 2 January 2024
• UNIX V6 memory layout
  ...y simple. The [[operating system]]'s [[kernel]] (both [[instruction]]s and data) permanently occupies low physical memory; [[process]]es reside above the k ...for one or two (see below) large block(s) containing the kernel's code and data; details of the kernel's address space and main memory layout are given bel
  7 KB (1,161 words) - 15:20, 8 July 2023
• KD11-E/EA microcode
  ...PU]] provide nice [[flow chart]]s for the [[microcode]] in these [[Central Processing Unit|CPUs]]; with one tiny exception, the microcode in the two is identical | 026 || 9-I || 322 || Fetch index data
  31 KB (3,760 words) - 05:02, 5 November 2022
• INTEL 80386 PROGRAMMER'S REFERENCE MANUAL
  Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i, Œ, trademark. MDS(R) is a registered trademark of Mohawk Data Sciences
  890 KB (107,817 words) - 03:20, 3 January 2024
• IBM OS2 1.0 announcement
  o Concurrent Processing of Multiple Applications of memory beyond 640KB for applications and data. End users will
  50 KB (7,113 words) - 03:35, 17 December 2018
• Inside OS/2
  Library of Congress Cataloging in Publication Data British Cataloging in publication Data available
  627 KB (92,395 words) - 03:42, 17 December 2018
• LSI-11
  ...ped in the Fall of 1975, was DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPU]], introducing the [[QBUS]], and using the [[LSI-11 chip set]]. It ...component side facing the viewer) is [[KEV11]], μROM 1, μROM 0, Control, Data Path.
  3 KB (411 words) - 22:06, 20 December 2023
• LSI-11/2
  ...s]], using the same [[LSI-11 chip set‎]]. It contains only the [[Central Processing Unit|CPU]], and nothing else; it is otherwise identical in functionality to ...ips (from the handle end) is, in fact, [[KEV11]], Control, uROM 1, uROM 0, Data Path (per the KD11-HA print set); the order given in the Handbook is that f
  2 KB (336 words) - 18:34, 19 July 2023
• UNIX* System V and 4.1C BSD
  void data type, and several bug fixes. The cc command including ged, a graphical editor, and numerous data
  113 KB (13,419 words) - 02:06, 17 December 2018
• MM11-L core memory
  * G110 - [[DEC card form factor|hex-width]] memory control logic and data channels ...planes wired to hold one or more MM11-L sets, in addition to the [[Central Processing Unit|CPU]].
  5 KB (841 words) - 07:14, 25 March 2022
• Small Peripheral Controller
  The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins ...] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which
  5 KB (868 words) - 23:38, 9 April 2022
• M9301 ROM
  It used four 4-bit wide [[PROM]]s to hold the data. The board occupied [[address]]es 773000-773776 and 765000-765776; a config Other configuration switches controlled which address the [[Central Processing Unit|CPU]] jumped to on power on (a clever kludge, controlled by another co
  9 KB (1,304 words) - 19:41, 7 December 2021
• KL10
  The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' (' ...alled; they connect to the E Bus (for control), and also to the C Bus (for data movement). The [[MASSBUS]] can be used to connect a variety of [[disk]] and
  11 KB (1,737 words) - 13:06, 2 April 2024
• KY11-LB Programmer's Console
  ...eripheral Controller|SPC]] slot in the same [[backplane]] as the [[Central Processing Unit|CPU]], and a 20-[[conductor]] [[flat cable]] which connected the two. ...d, a 6-digit [[Light Emitting Diode|LED]] display which showed address and data information, several individual indicator LEDs, and the following function
  7 KB (1,114 words) - 20:56, 24 October 2022
• FP11-B Floating-Point Processor
  .../70]] computers ([[KB11-A CPU|KB11-A]] and [[KB11-B CPU|KB11-B]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was the progenitor of the se * M8113 Exponent and Data Path
  1 KB (201 words) - 02:17, 13 October 2022
• FP11-C Floating-Point Processor
  ...uters (the later [[KB11-D CPU|KB11-D]] and [[KB11-C CPU|KB11-C]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was [[program compatible]] w * M8129 Exponent and Data Path
  1 KB (209 words) - 02:18, 13 October 2022
• Private Memory Interconnect
  ...roduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit|CPU]] and a [[KTJ11-B UNIBUS adapter|KTJ11-B]] [[UNIBUS]] adapter to c ...[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can re
  4 KB (731 words) - 17:11, 6 February 2024
• KT11-B Paging Option
  ...although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit|CPU]]'s address space) at any one time. ...anently dedicating scarce memory space in the Exec's address space to such data, or ii) having to change a number of page table entries in the Exec mode pa
  15 KB (2,571 words) - 22:23, 11 October 2022
• PDP-11 Memory Management
  The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User' An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called
  9 KB (1,311 words) - 18:10, 2 July 2023
• Virtual memory
  ...visible to to user as first-class objects, are supported in the [[Central Processing Unit|CPU]] (in the [[instruction]]s), etc; whereas pages are generally invi ...t size, measured in small units, is often stored in a field as part of the data which describes the segment to the CPU's hardware), whereas with variable p
  5 KB (876 words) - 20:01, 22 January 2024
• KA11 CPU
  The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP- * [[Data path|Data Paths]]
  9 KB (1,356 words) - 23:10, 29 February 2024
• KT11-B Technical Manual
  ...[[register]] names must be known, as well as the function of the [[Central Processing Unit|CPU]] and [[peripheral|device]] [[UNIBUS]]es, and also high-level inte [[Image:KT11-B_DataPaths.jpeg|450px|right|Main data paths]]
  31 KB (4,983 words) - 18:22, 2 July 2023
• KDJ11 CPUs
  There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset]]: ...even if that memory location is faulty - the CPU is getting the (correct) data from the cache.
  3 KB (457 words) - 14:32, 21 February 2023
• F-11 chip set
  ...P-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on ...although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)
  2 KB (384 words) - 23:50, 28 March 2022
• Central Processing Unit
  The '''Central Processing Unit''', usually abbreviated as '''CPU''', or simply called a '''processor' Instructions include data-handling instructions (such as arithmetic and logical operations), and cont
  1 KB (196 words) - 13:14, 5 November 2023
• MASSBUS
  ...ion (the 'Control Bus'), and a [[synchronous]] data transfer section (the 'Data Bus'). The two sections operate completely independently. ...sing Unit|CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bi
  5 KB (729 words) - 21:36, 2 December 2023
• LINC tape
  Instructions in the LINC [[Central Processing Unit|CPU]] could seek to a given block, and then read or write multiple blo The tape contained timing and mark tracks along with three data tracks; the first two allowed not only the ability to re-write individual b
  3 KB (519 words) - 02:13, 28 February 2024
• LINC-8
  ...a [[Direct Memory Access|DMA]] peripheral to the PDP-8, using the PDP-8 [[data break]] mechanism). A combined [[front panel]] allowed control of both CPUs
  2 KB (328 words) - 13:46, 11 July 2023
• Core memory
  ...ch uses tiny rings of magnetic material ('cores', hence the name) to store data; magnetized in one direction, such a core represents a '1' [[bit]], and in ...location in main memory, the location can be read out, with the [[Central Processing Unit|CPU]] telling the memory to wait before the write-back, so the CPU can
  8 KB (1,299 words) - 02:33, 4 March 2024
• Main memory
  '''Main memory''' refers to the [[memory]] from which the [[Central Processing Unit|CPU]] reads its [[instruction]]s as it [[execute]]s them; typically, a ...ata for immediate access by the CPU. Computers which keep instructions and data in the same memory are called 'von Neumann' [[architecture]]s; those which
  2 KB (250 words) - 17:10, 11 September 2019
• MK11 memory system
  ...erface boards (an M8158 address buffer board, and either an M8159 or M8164 data buffer board; the M8159 could only be used with 64KB memory modules, wherea [[Image:M8159MK11DBuf.jpg|thumb|250px|right|M8159 Data Buffer card (also with memory bus terminators)]]
  8 KB (1,276 words) - 03:23, 6 February 2024
• FIS floating point
  As with the FP11 version, it was tightly integrated with the [[Central Processing Unit|CPU]], so that the CPU processed a mix of 'regular' and floating point ...e|regular PDP-11 registers]] as a pointer to load and store floating point data from/to memory; floating point values could only be stored in [[main memory
  2 KB (355 words) - 17:49, 7 December 2021
• Microcode
  ...the functionality needed to control the internal operation of a [[Central Processing Unit|CPU]]. ...f the CPU's internal [[hardware]] elements during that microcycle: routing data out of [[register]]s (including internal registers not visible to the progr
  6 KB (853 words) - 14:25, 22 January 2024
• KE11-F Floating Instruction Set
  ...uad]] board, the M7239, which plugs into a pre-wired slot in the [[Central Processing Unit|CPU]] [[backplane]]. ...but it also uses microcode stored on the KE11-E, to control registers and data paths elsewhere.
  2 KB (246 words) - 02:34, 12 October 2022
• DH11 asynchronous serial line interface
  | DPR || OVR || FRM || PAR || colspan=4 | Line || colspan=8 | Data ...to the DH11 with a pair of BC08S cables, which carried the 'main' signals (data, etc - i.e. non-modem control); these cables were thus required for both 'l
  10 KB (1,443 words) - 02:27, 19 February 2023
• Non-Processor Request and Grant
  ...here; they are for a [[peripheral|device]] to gain control of the UNIBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. ...name comes from the fact that the device cannot request that the [[Central Processing Unit|CPU]] perform any action (i.e. an [[interrupt]]) while the device has
  1 KB (212 words) - 18:50, 6 July 2022
• Programmed I/O
  ...Processing Unit|CPU]], using [[instruction]]s performed by the CPU to move data - as opposed to [[Direct Memory Access|DMA]], in which the [[peripheral|dev ...', in which the CPU has to regularly check the device to see if it needs a data transfer, and ii) '''interrupt-driven''', where the device causes an [[inte
  1 KB (192 words) - 23:12, 20 October 2021
• KD11-E CPU
  [[Image:KD11-E M7265.jpg|250px|right|thumb|M7265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M7265''' Data Paths module and the '''M7266''' Control module. They plugged into a modifi
  5 KB (791 words) - 02:23, 6 December 2022
• KD11-EA CPU
  [[Image:KD11-EA M8265.jpg|250px|right|thumb|M8265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M8265''' Data Paths module and the '''M8266''' Control module.
  6 KB (1,045 words) - 22:47, 31 March 2022
• Cache
  ...a larger collection of data, implemented in such a way that access to the data copy in the cache is faster than to that in the large, full store. ...d disk blocks are kept in main memory, and network caches, where copies of data read from the network are kept on the local machine's disk.
  1 KB (251 words) - 00:58, 17 May 2023
• NORD-TSS
  ...ing the summer holidays of 1971, Bo Lewendal (system programmer at [[Norsk Data]]) implemented the initial version. It was further developed throughout 197 * Has a [[batch processing]] system
  1 KB (181 words) - 15:15, 9 September 2022
• VAXstation II
  {{InfoboxVAX-Data ...de); and the QBUS only for its [[input/output|I/O]] [[bus]]. Its [[Central Processing Unit|CPU]] was the [[MicroVAX II]]; the [[VCB01 Video Controller]] provided
  2 KB (254 words) - 16:59, 15 January 2024
• VAX 6000 Model 400
  {{InfoboxVAX-Data ...ange member of the [[VAX 6000 series]] line, the first to provide [[vector processing]].
  1 KB (151 words) - 15:01, 30 March 2023
• VAX 8300
  {{InfoboxVAX-Data The '''VAX 8200''' is a mid-range [[VAX]] dual-[[Central Processing Unit|CPU]] [[multi-processor]] system built around the [[VAX Bus Interconne
  2 KB (210 words) - 23:10, 28 March 2024
• VAX 8350
  {{InfoboxVAX-Data ...s an improved version of the [[VAX 8300]] mid-range [[VAX]] dual-[[Central Processing Unit|CPU]] [[multi-processor]] system built around the [[VAX Bus Interconne
  2 KB (201 words) - 23:11, 28 March 2024
• VAX 8700
  {{InfoboxVAX-Data The '''VAX 8700''' is a single-[[Central Processing Unit|CPU]] version of the [[VAX 8800]].
  2 KB (189 words) - 04:28, 13 January 2024
• VAX 8800
  {{InfoboxVAX-Data The '''VAX 8800''' is a dual-[[Central Processing Unit|CPU]] version of the [[VAX 8700]].
  2 KB (235 words) - 00:10, 2 January 2024
• VAX 88x0
  {{InfoboxVAX-Data ...computer models, the difference between them being the number of [[Central Processing Unit|CPUs]] installed in the basic cabinet:
  2 KB (204 words) - 04:31, 13 January 2024
• VAXstation 3520/3540
  {{InfoboxVAX-Data ...around a unique [[bus]], the [[M-bus]], to which is attached the [[Central Processing Unit|CPU]], [[main memory]], a [[graphics]] adaptor, and an [[input/output|
  3 KB (298 words) - 06:49, 17 April 2024

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