Difference between pages "DECtape" and "PDP-11 architecture"

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(Also 36-bit words.)
 
m (+see also, inst set extns)
 
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'''DECtape''' was a low-cost, low-capacity tape [[magnetic storage]] system intended for storage of small data entities (e.g. programs).  
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The '''[[PDP-11]]''' is a family of 16-bit [[minicomputer]] designed by [[DEC]], in production from 1970-1990. Although the basic [[address space]] was 16 bits, most models could hold more memory than that, although only a limited subset was visible to the program at any time.
  
−
It used 3/4-inch wide tape on small 4-inch reels, formatted before use into fixed-sized blocks which could be individually read or written. This differs from conventional [[magnetic tape]], which could only be written at the end of the previously-written area of the tape.
+
It had 8 general purpose [[register]]s; the operand coding, which was applied regularly across essentially the entire instruction set, allowed it to provide a two-address instruction architecture, not simple [[load-store architecture]] like its predecessor, the 12-bit [[PDP-8]].
  
−
DECtape was random access, so the drive had the ability to move forward and backwards to the desired block. The tape format included a block number at the start and end of each block, to help the drive find the desired block. Tapes could be read and written while moving in either direction, which meant that when seeking backwards to the target block, it was not necessary to bring the tape to a halt, and reverse it, before reading the data.
+
One of the registers was dedicated to be the [[Program Counter]], and one was more or less dedicated to be the [[Stack Pointer]]. (Other registers can be used as [[stack]] pointers, but the hardware uses this one for [[subroutine]] call and return, [[interrupt]]s, etc.)
  
−
DECtape also had exceptional reliability; it used a very simple and brute-force mechanism to produce that: it wrote all tracks in duplicate on each half of the tape. It was possible to punch a hole in a DECtape with a paper punch and leave the tape readable.
+
These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit words (and thus [[instruction]]s).
  
−
The drive had a single [[head]], and used hydro-dynamic lubrication to reduce wear on the tape; like disk heads, the tape floated on a layer of air while the tape was moving, without touching any metal. (In a test, a tape make 30,000 passes over a head without significant wear.)
+
The regular application of the operand coding across essentially the entire [[instruction set]] allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size.
  
−
DEC produced two DECtape drives; the single [[TU55]], and the dual [[TU56]]. Controllers for them existed for the [[PDP-8]], [[PDP-10]], [[PDP-11]] and [[PDP-15]], among others. Not all DECtape controllers supported reading in the reverse direction, however.
+
This was an important consideration both in the PDP-11's early life, when small and expensive [[core memory]] was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.
  
−
==History==
+
Most instructions come in both byte and word forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).
  
−
The predecessor of DECtape was [[LINC tape]], created in 1961 as the primary storage medium for the [[LINC]] computer.
+
==Extensions==
  
−
Although almost compatible (the drives on the [[PDP-12]] could support both LINC tapes and DECtapes), there were minor differences between the two: e.g. the location of the feed and take-up reels were reversed between the two, and the mark track format differed considerably, to support bi-directional read and write (the LINC tape could read and write in the forward direction only).
+
The first PDP-11 (the [[PDP-11/20]]) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware [[floating point]].
  
−
DECtape was originally called Microtape.  As a pun on this, IBM 7 and 9 track tape was sometimes called Macrotape.
+
The next model, the [[PDP-11/45]], added both of these (the latter as an option), although the follow-on low-cost machines, the [[PDP-11/05]] and [[PDP-11/04]], again did not have either.
  
−
==Tape format==
+
Later machines tended to include the former group - although on some early mid-range machines such as the [[PDP-11/40]] and [[PDP-11/03]], they were only an [[PDP-11 Extended Instruction Set|option]]. Floating point was also added to the later machines (although only as an option, until relatively late in the line).
  
−
The tape contained timing and mark tracks along with three data tracks; the first two allowed not only the ability to re-write individual blocks, but also meant that it could operate with varying tape speeds - the drives did not have capstans, so tape motion was controlled by the motors which drove the reels, and tape speed did vary considerably.
+
Late in the PDP-11 family's lifetime, a [[PDP-11 Commercial Instruction Set]] was defined, and made available as an option in some of the later machines.
  
−
Since each 'line' on the tape contained only three bits, a 12-bit word took four lines to store, and 16/18-bit words took 6 lines. (16-bit machines used 18-bit words on the tape, but normally ignored two of the bits.) Blocks were potentially of different sizes, but normally were all a single size: 128 12-bit words, 256 16/18-bit, or 128 36-bit words. A tape could hold 184K 12-bit words, or 144K 16/18-bit words.
+
===Floating point===
  
−
The block format included checksums, guard words to protect the block numbers, along with an inter-block zone. The tape format included end zones and extension areas on each end of the tape; the former was to prevent the tape running off the reels, and the latter to allow reel acceleration before reading/writing starts.
+
Two forms of floating point were added: a simplified form, [[FIS floating point]], with only the 4 basic operations, using 32-bit variables, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), [[FP11 floating point]].
  
−
==Specifications==
+
The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the [[PDP-11/45]] and variants thereof (the [[PDP-11/50]] and [[PDP-11/55]]), the [[PDP-11/70]], [[PDP-11/34]], [[PDP-11/44]] and [[PDP-11/23]]; it was standard in the [[KDJ11-B CPU|KDJ11-B]] and [[KDJ11-E CPU|KDJ11-E]] (although in all these machines an optional [[FPJ11 floating point accelerator]] greatly improved the floating point throughput).
  
−
* Tape - 3/4 inch x 260 feet; 1 mil Mylar sandwich tape (Mylar on both sides)
+
===Memory management===
−
* Tape speed - 97 inches/second (+/- 14 ips)
 
−
* Reading/writing rate - 30K lines/second (33-1/3 micro-seconds/line)
 
−
* Density - 350 lines/inch (+/- 55 lpi)
 
−
* Tape capacity - 147,968 16/18 bit words, in 578 blocks of 256 words each
 
−
* Start time - 150 milliseconds (+/- 15 msec)
 
−
* Stop time - 100 milliseconds (+/- 15 msec)
 
−
* Reverse time - 200 milliseconds (+/- 20 msec)
 
  
−
(Specifications may vary slightly between TU55 and TU56 transports.)
+
After a few disparate custom add-on units to provide [[memory management]] in the [[PDP-11/20]], memory management became [[PDP-11 Memory Management|standardized]] with the PDP-11/45 (in which it was an option); most later machines supported it. A simplified version was supported in the -11/40 and -11/23 (as an option), and in the -11/34 (standard).
 +
 
 +
==Operands==
 +
 
 +
The PDP-11 supported both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode. (Which is why PDP-11 [[object code]] is usually displayed in octal, as it is the optimal base for that, since each operand field will be in one octal 'digit'.)
 +
 
 +
As noted above, this operand form provided a large variety of operand types, including stack push and pop, literals, etc. This provides the basic instruction group with great flexibility, especially the double-operand instructions (MOV, ADD, etc).
 +
 
 +
A few instructions (mostly those which were added to the instruction repertoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. if not already in a register, that operand must be pre-loaded into one by another instruction).
 +
 
 +
===Addressing modes===
 +
 
 +
The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes. The indirect bit is the low bit, so odd values of the mode 'digit' are indirect.
 +
 
 +
The 'regular' modes are:
 +
 
 +
{| border=1
 +
! Mode !! Name                        !! Symbolic    !! Description
 +
|-
 +
|0      || Register                    || R            || (R) is the operand
 +
|-
 +
|2      || Auto-increment              || (R)+        || (R) is the address; (R) is incremented by 1 or 2, in case of byte or word instructions.
 +
|-
 +
|4      || Auto-decrement              || (R)-        || (R) is decremented by 1 or 2, in case of byte or word instructions; R is address.
 +
|-
 +
|6      || Index                        || X(R)        || (R) + X is the address.
 +
|}
 +
 
 +
and the indirect modes are:
 +
 
 +
{| border=1
 +
! Mode !! Name                        !! Symbolic    !! Description
 +
|-
 +
|1      || Register deferred            || @R or (R)    || (R) contains address of operand
 +
|-
 +
|3      || Auto-increment deferred      || @(R)+        || (R) is the address of the address; (R) is incremented by 2
 +
|-
 +
|5      || Auto-decrement deferred      || @(R)-        || (R) is decremented by two; (R) is the address of the address.
 +
|-
 +
|7      || Index deferred              || @X(R)        || (R) + X is the address of the address
 +
|}
 +
 
 +
As mentioned, auto-increment and auto-decrement allow any register to be used as a stack pointer, but the hardware enforces the use of R6 as the SP, so it is un-common for another register to be used for this.
 +
 
 +
The use of auto-increment mode with the PC provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for [[location-independent code]].
 +
 
 +
==Instruction set==
 +
 
 +
The instruction set provided a number of double-operand instructions:
 +
 
 +
* MOV
 +
* ADD
 +
* SUB
 +
* BIT (bit test)
 +
* BIS (bit set)
 +
* BIC (bit clear)
 +
 
 +
(as noted, ADD and SUB are only available in word mode), and many single-operand instructions:
 +
 
 +
* CLR
 +
* TST (compare with 0)
 +
* INC
 +
* DEC
 +
* NEG
 +
* COM (complement)
 +
* ASR (arithmetic shift right)
 +
* ASL
 +
* ROR (rotate right)
 +
* ROL
 +
* SWAB (swap bytes)
 +
* ADC (add carry)
 +
* SBC
 +
 
 +
===Condition codes and conditional branches===
 +
 
 +
The instruction set provided a plethora of branches, although all branches are limited to a range of 127 words before or after the current instruction; a limit which is not onerous in practise. All the [[conditional branch]]es depend on a prior instruction to set 4 [[condition codes]] (stored in the [[Processor Status Word]]):
 +
 
 +
* Z - Zero
 +
* N - Negative (i.e. high bit set)
 +
* C - Carry
 +
* V - Overflow
 +
 
 +
Conditional branches:
 +
 
 +
* BR (un-conditional)
 +
* BNE (non-zero)
 +
* BEQ (zero)
 +
* BMI (negative)
 +
* BPL (positive)
 +
* BVC (overflow clear)
 +
* BVS (overflow)
 +
* BCS (carry)
 +
* BCC (no carry)
 +
 
 +
Signed branches:
 +
 
 +
* BGE (greater than or equal to 0)
 +
* BGT
 +
* BLE
 +
* BLT
 +
 
 +
Unsigned branches:
 +
 
 +
* BHIS (higher than, or the same)
 +
* BHI
 +
* BLOS
 +
* BLO
 +
 
 +
===Miscellaneous===
 +
 
 +
Other flow of control instructions (both JMP and JSR) can transfer to any location in the address space):
 +
 
 +
* JMP
 +
* JSR - subroutine call
 +
* RTS - subroutine return
 +
 
 +
A variety of other instructions (e.g. to [[trap]] to the [[operating system]], halt the CPU, etc) also exist.
 +
 
 +
===Added later===
 +
 
 +
The PDP-11/45 added a few miscellaneous instructions:
 +
 
 +
* SOB (decrement and conditionally branch)
 +
* XOR (word only, and also only provides a register number for one operand)
 +
* SXT (sign extend, word only)
 +
* MARK (subroutine argument setup)
 +
* RTT (return from interrupt while inhibiting 'trace' trap)
 +
* SPL (set CPU priority level)
 +
 
 +
All of these, with the exception of SPL, appeared in all later models (except the -11/05 and -11/04).
 +
 
 +
Various later models added various instructions for [[Processor Status Word]] access, maintenance, etc.
 +
 
 +
==Virtualization==
 +
 
 +
The PDP-11 is impossible to [[virtual machine|virtualize]], since there are a number instructions used by operating systems which do not trap when executed by a program running in user mode. HALT does trap, but not others, including:
 +
 
 +
* RESET
 +
* WAIT
 +
* RT[IT]
 +
* SPL
 +
* M[TF]P[ID]
 +
* M[TF]PS
 +
 
 +
Of these, in user mode RESET is a [[no-op]], RT[IT] cannot change the current and previous modes, MFPI acts like MPFD in user mode when the previous mode is also user (to prevent 'theft' of proprietary code), and MTPS can only set the condition codes.
 +
 
 +
==See also==
 +
 
 +
* [[PDP-11 Memory Management]]
 +
* [[PDP-11 Extended Instruction Set]]
 +
* [[PDP-11 Commercial Instruction Set]]
 +
 
 +
{{PDP-11}}
 +
 
 +
[[Category: PDP-11s]]
 +
[[Category: DEC Architectures]]

Revision as of 03:48, 18 December 2018

The PDP-11 is a family of 16-bit minicomputer designed by DEC, in production from 1970-1990. Although the basic address space was 16 bits, most models could hold more memory than that, although only a limited subset was visible to the program at any time.

It had 8 general purpose registers; the operand coding, which was applied regularly across essentially the entire instruction set, allowed it to provide a two-address instruction architecture, not simple load-store architecture like its predecessor, the 12-bit PDP-8.

One of the registers was dedicated to be the Program Counter, and one was more or less dedicated to be the Stack Pointer. (Other registers can be used as stack pointers, but the hardware uses this one for subroutine call and return, interrupts, etc.)

These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit words (and thus instructions).

The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size.

This was an important consideration both in the PDP-11's early life, when small and expensive core memory was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.

Most instructions come in both byte and word forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).

Extensions

The first PDP-11 (the PDP-11/20) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware floating point.

The next model, the PDP-11/45, added both of these (the latter as an option), although the follow-on low-cost machines, the PDP-11/05 and PDP-11/04, again did not have either.

Later machines tended to include the former group - although on some early mid-range machines such as the PDP-11/40 and PDP-11/03, they were only an option. Floating point was also added to the later machines (although only as an option, until relatively late in the line).

Late in the PDP-11 family's lifetime, a PDP-11 Commercial Instruction Set was defined, and made available as an option in some of the later machines.

Floating point

Two forms of floating point were added: a simplified form, FIS floating point, with only the 4 basic operations, using 32-bit variables, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), FP11 floating point.

The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the PDP-11/45 and variants thereof (the PDP-11/50 and PDP-11/55), the PDP-11/70, PDP-11/34, PDP-11/44 and PDP-11/23; it was standard in the KDJ11-B and KDJ11-E (although in all these machines an optional FPJ11 floating point accelerator greatly improved the floating point throughput).

Memory management

After a few disparate custom add-on units to provide memory management in the PDP-11/20, memory management became standardized with the PDP-11/45 (in which it was an option); most later machines supported it. A simplified version was supported in the -11/40 and -11/23 (as an option), and in the -11/34 (standard).

Operands

The PDP-11 supported both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode. (Which is why PDP-11 object code is usually displayed in octal, as it is the optimal base for that, since each operand field will be in one octal 'digit'.)

As noted above, this operand form provided a large variety of operand types, including stack push and pop, literals, etc. This provides the basic instruction group with great flexibility, especially the double-operand instructions (MOV, ADD, etc).

A few instructions (mostly those which were added to the instruction repertoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. if not already in a register, that operand must be pre-loaded into one by another instruction).

Addressing modes

The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes. The indirect bit is the low bit, so odd values of the mode 'digit' are indirect.

The 'regular' modes are:

Mode Name Symbolic Description
0 Register R (R) is the operand
2 Auto-increment (R)+ (R) is the address; (R) is incremented by 1 or 2, in case of byte or word instructions.
4 Auto-decrement (R)- (R) is decremented by 1 or 2, in case of byte or word instructions; R is address.
6 Index X(R) (R) + X is the address.

and the indirect modes are:

Mode Name Symbolic Description
1 Register deferred @R or (R) (R) contains address of operand
3 Auto-increment deferred @(R)+ (R) is the address of the address; (R) is incremented by 2
5 Auto-decrement deferred @(R)- (R) is decremented by two; (R) is the address of the address.
7 Index deferred @X(R) (R) + X is the address of the address

As mentioned, auto-increment and auto-decrement allow any register to be used as a stack pointer, but the hardware enforces the use of R6 as the SP, so it is un-common for another register to be used for this.

The use of auto-increment mode with the PC provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for location-independent code.

Instruction set

The instruction set provided a number of double-operand instructions:

  • MOV
  • ADD
  • SUB
  • BIT (bit test)
  • BIS (bit set)
  • BIC (bit clear)

(as noted, ADD and SUB are only available in word mode), and many single-operand instructions:

  • CLR
  • TST (compare with 0)
  • INC
  • DEC
  • NEG
  • COM (complement)
  • ASR (arithmetic shift right)
  • ASL
  • ROR (rotate right)
  • ROL
  • SWAB (swap bytes)
  • ADC (add carry)
  • SBC

Condition codes and conditional branches

The instruction set provided a plethora of branches, although all branches are limited to a range of 127 words before or after the current instruction; a limit which is not onerous in practise. All the conditional branches depend on a prior instruction to set 4 condition codes (stored in the Processor Status Word):

  • Z - Zero
  • N - Negative (i.e. high bit set)
  • C - Carry
  • V - Overflow

Conditional branches:

  • BR (un-conditional)
  • BNE (non-zero)
  • BEQ (zero)
  • BMI (negative)
  • BPL (positive)
  • BVC (overflow clear)
  • BVS (overflow)
  • BCS (carry)
  • BCC (no carry)

Signed branches:

  • BGE (greater than or equal to 0)
  • BGT
  • BLE
  • BLT

Unsigned branches:

  • BHIS (higher than, or the same)
  • BHI
  • BLOS
  • BLO

Miscellaneous

Other flow of control instructions (both JMP and JSR) can transfer to any location in the address space):

  • JMP
  • JSR - subroutine call
  • RTS - subroutine return

A variety of other instructions (e.g. to trap to the operating system, halt the CPU, etc) also exist.

Added later

The PDP-11/45 added a few miscellaneous instructions:

  • SOB (decrement and conditionally branch)
  • XOR (word only, and also only provides a register number for one operand)
  • SXT (sign extend, word only)
  • MARK (subroutine argument setup)
  • RTT (return from interrupt while inhibiting 'trace' trap)
  • SPL (set CPU priority level)

All of these, with the exception of SPL, appeared in all later models (except the -11/05 and -11/04).

Various later models added various instructions for Processor Status Word access, maintenance, etc.

Virtualization

The PDP-11 is impossible to virtualize, since there are a number instructions used by operating systems which do not trap when executed by a program running in user mode. HALT does trap, but not others, including:

  • RESET
  • WAIT
  • RT[IT]
  • SPL
  • M[TF]P[ID]
  • M[TF]PS

Of these, in user mode RESET is a no-op, RT[IT] cannot change the current and previous modes, MFPI acts like MPFD in user mode when the previous mode is also user (to prevent 'theft' of proprietary code), and MTPS can only set the condition codes.

See also


v • d • e PDP-11 Computers and Peripherals
UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70
PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94

QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93

QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E

Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI

Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management

UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U

Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11

Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11

CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B

Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store

Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P

More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS

PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150   CTI PDP-11s - PRO-325 • PRO-350 • PRO-380

Clones: CM 1420 • SM 1420

Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences

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