Difference between pages "Running UNIX V6 on an -11/23" and "PDP-11 Memory Management"

From Computer History Wiki
(Difference between pages)
Jump to: navigation, search
(For now, insts - will add links later)
 
m (+cat)
 
Line 1: Line 1:
−
It is possible to run [[UNIX Sixth Edition]] on a [[PDP-11/23]], although this is not a configuration supported 'out of the box' with the Version 6 distribution.
+
[[PDP-11]]s which provide [[memory management]] use a standard '''PDP-11 Memory Management''' architecture. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '''segments'''; each segment of the virtual address space can be assigned to any location in physical [[main memory]].
  
−
There are three issues which have to be addressed before V6 will run on a /23:
+
Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow down (from higher addresses to lower).
  
−
* The lack of a [[console]] [[switch register]]
+
The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate set of mapping [[register]]s, to provide separate virtual address spaces for each mode.
−
* The lack (normally) of a clock
 
−
* The ability of the /23 to have more than 256KB of [[main memory]]
 
  
−
All of them are fairly simple to deal with, but they require minor modifications to the system, so you will need a running V6 to do these; bringing it under a simulator, e.g. [[Installing UNIX Sixth Edition on Ersatz-11]], is therefore required.
+
An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called '''Split I+D space''' capability; this increases the memory available to the operating system, and each user, to 128 Kbytes.
  
−
Use the 'm40.s' machine language file, as the [[PDP-11 Memory Management|memory management]] supported by the /23 is the same 'simple' kind (i.e. without split I+D) as that on the [[PDP-11/40]].
+
(Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.)
  
−
==Switch register==
+
When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.
  
−
V6 expects to see a switch register, and refers to it during [[booting]] to see whether to come up [[single-user]] or not.
+
If any instruction causes a [[fault]] (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory management [[trap]] occurs.
  
−
The best general approach is to provide a 'software switch register'; a location in low memory whose contents are used as the switch register.
+
===Simplified subset===
  
−
The following can be used to do so:
+
A number of the smaller PDP-11's (notably the [[PDP-11/40]], [[PDP-11/34]], [[PDP-11/23]] and [[PDP-11/24]]) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).
  
−
* insert four lines into l.s (in the appropriate location in the source):
+
Also, there is no SSR1 register (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which auto-increment the same register several times).
  
−
<pre>
+
==Registers==
−
. = 50^.
 
−
.globl  _SW
 
−
_SW:    memcsw
 
−
memcsw: 173030
 
−
</pre>
 
  
−
* change the last line of param.h to read:
+
The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which use page tables held in main memory, and cached in the CPU).
  
−
<pre>
+
===Control===
−
extern int *SW;
 
−
</pre>
 
  
−
* add the following three lines to main.c (last two go just after
+
There are four registers which control the overall operation of the Memory Management Unit:
−
the check for the LTC)
 
  
−
<pre>
+
{| class="wikitable"
−
#define SWREG 0177570
+
! Address !! Name !! Function
 +
|-
 +
| 777572 || SSR0 || Control and status
 +
|-
 +
| 777574 || SSR1 || Register increment/descrement record
 +
|-
 +
| 777576 || SSR2 || Virtual address associated with the fault (usually the instruction address)
 +
|-
 +
| 777516 || SSR3 || D-space enable/disable (per mode)
 +
|}
  
−
if (fuiword(SWREG) != -1)
+
On the 'simplified subset' machines, SSR1 and SSR3 are not implemented.
−
SW = SWREG;
 
−
</pre>
 
  
−
* then recompile sys4.c and prf.c, plus the two files above.
+
SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved). The layout of SSR0 is:
 +
{{16bit-header}}
 +
| Non-resident || Length || Read-only || Trap || colspan=2 | Unused || Enable Trap || Maintenance || Instruction Completed || colspan=2 | CPU Mode || I/D || colspan=3 | Page || Enable
 +
{{16bit-bitout}}
  
−
==Clock==
+
When any of the first three bits (all error aborts) are set, bits 1-7, as well as SSR1 and SSR2, are frozen. On the 'simplified subset' machines, bits 12, 9, 7 and 4 are not implemented.
  
−
V6 requires either a [[KW11-L]] or [[KW11-P]] clock, and will 'panic' unless one or the other is found. The -11/23 does have a 60Hz clock, but... there is no control register. There are two ways to deal with this:
+
SSR1 contains information about register modifications (given there in [[two's complement]]) performed during the course of an instruction, to allow those modifications to be 'backed out' if the instruction needs to be restarted after a memory management fault. Its layout is:
 +
{{16bit-header}}
 +
| colspan=5 | Change || colspan=3 | Register || colspan=5 | Change || colspan=3 | Register
 +
{{16bit-bitout}}
  
−
# Install a [[BDV11]] card, which has a simulation of the KW11-L on it, or
+
SSR2 contains the address of the instruction which caused the memory management fault.
−
# Modify the OS
 
  
−
To do the latter, in main.c, change:
+
SSR3 contains bits to enable Split I+D in the three modes; on machines which have [[UNIBUS map]]s, the enable for it is also here. Its layout is:
 +
{{16bit-header}}
 +
| colspan=10 | Unused || Enable UNIBUS Map || Enable 22-bit || Unused || Kernel || Supervisor || User
 +
{{16bit-bitout}}
  
−
<pre>
+
The 'Enable 22-bit' bit only applies on machines which support larger memories, i.e. the [[PDP-11/70]], [[PDP-11/44]], and machines with the [[KDF11 CPUs]] and [[KDJ11 CPUs]].
−
panic("no clock");
 
−
</pre>
 
  
−
to:
+
===PARs and PDRs===
  
−
<pre>
+
Each segment (up to 48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register (PAR).
−
{
 
−
lks = 0;
 
−
printf("No clock?\n");
 
−
printf("On an 11/23, turn on clock now.\n");
 
−
}
 
−
</pre>
 
  
−
and change the:
+
The PAR contains the base physical address for the segment (in units of 0100/64. bytes). On machines which have only [[UNIBUS]] memory (e.g. PDP-11/40, [[PDP-11/45]], etc) these registers are 12 bits long, since the maximum amount of physical memory on these machines is 248 Kbytes. On machines which support up to 4 MBytes of physical memory (e.g. [[PDP-11/70]], [[PDP-11/44]], PDP-11/23, etc), they are 16 bits long.
  
−
<pre>
+
The PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by the hardware), etc. The layout of the PDR is:
−
*lks = 0115;
 
−
</pre>
 
  
−
to:
+
{{16bit-header}}
 +
| Unused || colspan=7 | Length || Trapped || Written || colspan=2 | Unused || Direction || colspan=3 | Access Control
 +
{{16bit-bitout}}
  
−
<pre>
+
The values of the 'Access Control' field are:
−
if (lks != 0)
+
{| class="wikitable"
−
*lks = 0115;
+
! Value !! Mode
−
</pre>
+
|-
 +
| 0 || Non-resident - abort all accesses
 +
|-
 +
| 1 || Read-only watched - abort on write, trap on read
 +
|-
 +
| 2 || Read-only - abort on write
 +
|-
 +
| 3 || Unused, reserved - abort all accesses
 +
|-
 +
| 4 || Read/write all watched - trap on read or write
 +
|-
 +
| 5 || Read/write watched - trap on write
 +
|-
 +
| 6 || Read/write - none
 +
|-
 +
| 7 || Unused, reserved - abort all accesses
 +
|}
  
−
'''''NOTE:''''' It is '''critical''' to turn ''off'' the system's clock (usually possible with a switch on the console) before and during booting, as a clock [[interrupt]] before UNIX is ready for it can trash the system (and has been observed to trash the disk, if you are really unlucky).
+
On the 'simplified subset' machines, only modes 0, 2 and 6 are supported, and neither is the 'Trapped' bit (set on PDR's for memory references that trapped, on the other machines).
  
−
==Larger main memory==
+
The addresses of the PAR/PDR sets are:
  
−
All -11/23's after the (very rare) model A can support more than 256KB of main memory. If you put more than 256KB on an -11/23 and boot V6, it will ignore the extra memory above 256KB (technically, above 248KB).
+
{| class="wikitable"
 +
! Address !! Name !! Function
 +
|-
 +
| 772200 || SISD0 || Supervisor I-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772216 || SISD7 || Supervisor I-Space PDR #7
 +
|-
 +
| 772220 || SDSD0 || Supervisor D-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772236 || SDSD7 || Supervisor D-Space PDR #7
 +
|-
 +
| 772240 || SISA0 || Supervisor I-Space PAR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772256 || SISA7 || Supervisor I-Space PAR #7
 +
|-
 +
| 772260 || SDSA0 || Supervisor D-Space PAR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772276 || SDSA7 || Supervisor D-Space PAR #7
 +
|-
 +
| 772300 || KISD0 || Kernel I-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772316 || KISD7 || Kernel I-Space PDR #7
 +
|-
 +
| 772320 || KDSD0 || Kernel D-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772336 || KDSD7 || Kernel D-Space PDR #7
 +
|-
 +
| 772340 || KISA0 || Kernel I-Space PAR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772356 || KISA7 || Kernel I-Space PAR #7
 +
|-
 +
| 772360 || KDSA0 || Kernel D-Space PAR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 772376 || KDSA7 || Kernel D-Space PAR #7
 +
|-
 +
| 777600 || UISD0 || User I-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 777616 || UISD7 || User I-Space PDR #7
 +
|-
 +
| 777620 || UDSD0 || User D-Space PDR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 777636 || UDSD7 || User D-Space PDR #7
 +
|-
 +
| 777640 || UISA0 || User I-Space PAR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 777656 || UISA7 || User I-Space PAR #7
 +
|-
 +
| 777660 || UDSA0 || User D-Space PAR #0
 +
|-
 +
| colspan="2" style="text-align:center;" | ...
 +
|-
 +
| 777676 || UDSA7 || User D-Space PAR #7
 +
|}
  
−
That is because 22-bit operation must be explicitly enabled, using [[PDP-11 Memory Management|SSR3]]. So, make a copy of m40.s (m23.s seems the obvious name), and add the following:
+
{{PDP-11}}
  
−
<pre>
+
[[Category: PDP-11s]]
−
mov    $EN22BIT, *$SSR3 / allow > 256KB
 
−
</pre>
 
−
 
 
−
just before the
 
−
 
 
−
<pre>
 
−
inc SSR0
 
−
</pre>
 
−
 
 
−
You will also need to add:
 
−
 
 
−
<pre>
 
−
SSR3 = 172516
 
−
EN22BIT = 20
 
−
</pre>
 
−
 
 
−
somewhere (probably at the end, with the other register definitions).
 
−
 
 
−
Finally, the [[PDP-11 Memory Management|PAR]] contents to reach the I/0 page are different in a 22-bit system from an 18-bit system, so change:
 
−
 
 
−
<pre>
 
−
IO = 7600
 
−
</pre>
 
−
 
 
−
to:
 
−
 
 
−
<pre>
 
−
IO = 177600
 
−
</pre>
 
−
 
 
−
Edit the 'run' file that builds the system to use m23.o instead of m40.o, and that should do it.
 

Revision as of 15:58, 17 February 2018

PDP-11s which provide memory management use a standard PDP-11 Memory Management architecture. When memory management is enabled, the basic 64 Kbyte address space of the PDP-11 architecture is divided into 8 segments; each segment of the virtual address space can be assigned to any location in physical main memory.

Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 stacks, which typically grow down (from higher addresses to lower).

The CPU can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate set of mapping registers, to provide separate virtual address spaces for each mode.

An additional enhancement is that instruction and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called Split I+D space capability; this increases the memory available to the operating system, and each user, to 128 Kbytes.

(Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.)

When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.

If any instruction causes a fault (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory management trap occurs.

Simplified subset

A number of the smaller PDP-11's (notably the PDP-11/40, PDP-11/34, PDP-11/23 and PDP-11/24) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).

Also, there is no SSR1 register (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which auto-increment the same register several times).

Registers

The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which use page tables held in main memory, and cached in the CPU).

Control

There are four registers which control the overall operation of the Memory Management Unit:

Address Name Function
777572 SSR0 Control and status
777574 SSR1 Register increment/descrement record
777576 SSR2 Virtual address associated with the fault (usually the instruction address)
777516 SSR3 D-space enable/disable (per mode)

On the 'simplified subset' machines, SSR1 and SSR3 are not implemented.

SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved). The layout of SSR0 is:

Non-resident Length Read-only Trap Unused Enable Trap Maintenance Instruction Completed CPU Mode I/D Page Enable
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

When any of the first three bits (all error aborts) are set, bits 1-7, as well as SSR1 and SSR2, are frozen. On the 'simplified subset' machines, bits 12, 9, 7 and 4 are not implemented.

SSR1 contains information about register modifications (given there in two's complement) performed during the course of an instruction, to allow those modifications to be 'backed out' if the instruction needs to be restarted after a memory management fault. Its layout is:

Change Register Change Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

SSR2 contains the address of the instruction which caused the memory management fault.

SSR3 contains bits to enable Split I+D in the three modes; on machines which have UNIBUS maps, the enable for it is also here. Its layout is:

Unused Enable UNIBUS Map Enable 22-bit Unused Kernel Supervisor User
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The 'Enable 22-bit' bit only applies on machines which support larger memories, i.e. the PDP-11/70, PDP-11/44, and machines with the KDF11 CPUs and KDJ11 CPUs.

PARs and PDRs

Each segment (up to 48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register (PAR).

The PAR contains the base physical address for the segment (in units of 0100/64. bytes). On machines which have only UNIBUS memory (e.g. PDP-11/40, PDP-11/45, etc) these registers are 12 bits long, since the maximum amount of physical memory on these machines is 248 Kbytes. On machines which support up to 4 MBytes of physical memory (e.g. PDP-11/70, PDP-11/44, PDP-11/23, etc), they are 16 bits long.

The PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by the hardware), etc. The layout of the PDR is:


Unused Length Trapped Written Unused Direction Access Control
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The values of the 'Access Control' field are:

Value Mode
0 Non-resident - abort all accesses
1 Read-only watched - abort on write, trap on read
2 Read-only - abort on write
3 Unused, reserved - abort all accesses
4 Read/write all watched - trap on read or write
5 Read/write watched - trap on write
6 Read/write - none
7 Unused, reserved - abort all accesses

On the 'simplified subset' machines, only modes 0, 2 and 6 are supported, and neither is the 'Trapped' bit (set on PDR's for memory references that trapped, on the other machines).

The addresses of the PAR/PDR sets are:

Address Name Function
772200 SISD0 Supervisor I-Space PDR #0
...
772216 SISD7 Supervisor I-Space PDR #7
772220 SDSD0 Supervisor D-Space PDR #0
...
772236 SDSD7 Supervisor D-Space PDR #7
772240 SISA0 Supervisor I-Space PAR #0
...
772256 SISA7 Supervisor I-Space PAR #7
772260 SDSA0 Supervisor D-Space PAR #0
...
772276 SDSA7 Supervisor D-Space PAR #7
772300 KISD0 Kernel I-Space PDR #0
...
772316 KISD7 Kernel I-Space PDR #7
772320 KDSD0 Kernel D-Space PDR #0
...
772336 KDSD7 Kernel D-Space PDR #7
772340 KISA0 Kernel I-Space PAR #0
...
772356 KISA7 Kernel I-Space PAR #7
772360 KDSA0 Kernel D-Space PAR #0
...
772376 KDSA7 Kernel D-Space PAR #7
777600 UISD0 User I-Space PDR #0
...
777616 UISD7 User I-Space PDR #7
777620 UDSD0 User D-Space PDR #0
...
777636 UDSD7 User D-Space PDR #7
777640 UISA0 User I-Space PAR #0
...
777656 UISA7 User I-Space PAR #7
777660 UDSA0 User D-Space PAR #0
...
777676 UDSA7 User D-Space PAR #7


v • d • e PDP-11 Computers and Peripherals
UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70
PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94

QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93

QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E

Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI

Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management

UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U

Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11

Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11

CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B

Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store

Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P

More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS

PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150   CTI PDP-11s - PRO-325 • PRO-350 • PRO-380

Clones: CM 1420 • SM 1420

Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences

Retrieved from "https://gunkies.org/w/index.php?title=Running_UNIX_V6_on_an_-11/23&oldid=15635"