KB11-D CPU

The KB11-D CPU is the later CPU for the PDP-11/45; it differed from the earlier KB11-A CPU in that is used the synchronous FP11-C Floating-Point Processor as its optional FPP. Both that and the optional KT11-C Memory Management Unit plugged into the CPU's backplane.

In addition to main memory on the UNIBUS, the KB11-A could also use high-speed MOS or bipolar memory, specific to the PDP-11/45, which plugged into a special bus, the Fastbus, which was also part of the CPU's backplane.

Boards

The KB11-D board set included many of the same boards as the KB11-A CPU:

• M8100 Data and Address Paths
• M8101 General Register and Control
• M8104 Processor Data and UNIBUS Registers
• M8105 Timing and Miscellaneous Control
• M8109 Timing Generator

with the following differences:

• The M8102 Instruction Register and Decode was replaced with the M8132
• The M8103 ROM and ROM Control was replaced with the M8123
• The M8106 UNIBUS and Console Control was replaced with the M8119

(Note that the M8132 and M8123 are shared with the KB11-C CPU of the PDP-11/70.)

In addition, the CPU includes either:

• M8116 Segmentation Jumper Board

used when the KT11-C Memory Management Unit (termed the KT11-CD in this CPU) is not present, or:

• M8107 Segmentation Address Paths
• M8108-YA Segmentation Status Registers

which comprise the KT11-CD (the M8108 Segmentation Status Registers board of the KT11-C was replaced with the M8108-YA variant).

Documentation

• EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual