Difference between revisions of "PDP-11/74"
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It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]). | It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]). | ||
| − | The CPU was the [[KB11-E CPU]], a modified version of the [[KB11-C CPU]] of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private [[bus]], allowed one CPU to interrupt or [[bootstrap]] another CPU. A multi-ported high-resolution 'Time of Day' [[clock]] was also provided. Also, the ASRB instruction was modified to be [[atomic]], for synchronization between CPUs. | + | The CPU was the [[KB11-E CPU]], a modified version of the [[KB11-C CPU]] of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private [[bus]], allowed one CPU to [[interrupt]] or [[bootstrap]] another CPU. A multi-ported high-resolution 'Time of Day' [[clock]] was also provided. Also, the ASRB instruction implementation was modified to be [[atomic]], for use in synchronization between CPUs. |
There was also a planned [[Commercial Instruction Set]] processor, the CISP. | There was also a planned [[Commercial Instruction Set]] processor, the CISP. | ||
Revision as of 11:55, 20 August 2018
The PDP-11/74 was a tightly-coupled symmetric multi-processor version of the PDP-11/70; it could hold from two to four CPUs.
It used a multi-port memory version of the MK11 memory system, the MKA11. Some devices, such as disks and magnetic tape drives, could be shared between two of the CPUs, using the multi-port capabilities of many MASSBUS devices; other devices (e.g. UNIBUS devices) could not be shared (other than via software, or use of a UNIBUS switch).
The CPU was the KB11-E CPU, a modified version of the KB11-C CPU of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private bus, allowed one CPU to interrupt or bootstrap another CPU. A multi-ported high-resolution 'Time of Day' clock was also provided. Also, the ASRB instruction implementation was modified to be atomic, for use in synchronization between CPUs.
There was also a planned Commercial Instruction Set processor, the CISP.
A significant run of prototypes were produced, and the RSX-11 operating system was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly because of concern that with its very high I/O bandwidth, it would compete with the new VAX-11/780), and never appeared as a product.
| v • d • e PDP-11 Computers and Peripherals |
|---|
| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
