Difference between revisions of "F-11 chip set"

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The '''F-11 chip set''' (code-named 'Fonz') was [[DEC]]'s second microprocessor implementation of the [[PDP-11 architecture]]. It was used in the [[KDF11 CPUs]].
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[[Image:m8186.jpg|250px|thumb|right|F-11 chip set on a [[KDF11-A CPU|KDF11-A]]]]
  
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The main CPU was implemented in two chips (carried on a single DIP carrier): the data paths chip (DC302, DEC part # 21-15541-Ax, where x is a capital letter giving the revision; B is the most common, although C has been seen), which contains the registers, ALU, etc; and the control chip (DC303, DEC part # 23-001C7-Ax, although only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic.
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The '''F-11 chip set''' (code-named 'Fonz') was [[DEC]]'s second [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on a single [[Dual Inline Package|DIP]] carrier).
  
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Unlike the first microprocessor implementation (the [[LSI-11]]), the F-11 chip set implemented the full PDP-11 architecture, including the optional [[KTJ11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible floating point. (The KEF11-A requires the KTJ11-A, since the floating point registers are actually in the KTJ11-A; probably because the KEF11-A is microcode, and there aren't enough pins for both the data bus, and the microcode bus.) There is also a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS).
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Unlike the first microprocessor implementation (the [[LSI-11]]), the full F-11 chip set implemented the full PDP-11 architecture, including the optional [[KTF11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible [[floating point]].
  
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The KTJ11-A chip was the DC304, DEC part # 21-15542-0n (where n is a digit giving the revision; 0 and 1 have been seen); the KEF11-A is another dual carrier (with the chips being DEC part # 23-002C7-Ax and DEC part # 23-003C7-Ax; only the A revision of both has been seen).
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(The KEF11-A requires the KTF11-A, since the floating point [[register]]s are actually in the KTF11-A. The reason why is not known; although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)
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There is also a double-width 6-chip carrier, the [[KEF11-B CIS chip]], which implements the [[PDP-11 Commercial Instruction Set]] (CIS); not all KDF11 CPUs can hold this, though.
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==Chip versions==
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The data paths chip is the DC302, [[DEC part number]] 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, [[Arithmetic logic unit|ALU]], etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).
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==ODT limitations==
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The F-11 chip set includes microcode which provides 'front panel' functionality named '[[QBUS CPU ODT|ODT]]'; the ability to read and write to [[main memory]], start the processor, etc. However, the original version of the KDF11-A only supported 18-bit [[address]]ing, and even though later versions supported 22-bit addressing, ODT in the KDF11's was always limited to 18-bit addressing: i.e. it is impossible to interact with memory above 256 Kbytes from ODT.
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The later [[KDJ11 CPUs]] do not have this limitation.
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==See also==
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* [[J-11 chip set]]
  
 
==External links==
 
==External links==
  
 
* [http://simh.trailing-edge.com/semi/f11.html F-11 (1979)]
 
* [http://simh.trailing-edge.com/semi/f11.html F-11 (1979)]
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{{stub}}
 
  
 
{{PDP-11}}
 
{{PDP-11}}
  
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[[Category:DEC processors]]
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[[Category:PDP-11 Processors]]

Latest revision as of 22:50, 28 March 2022

F-11 chip set on a KDF11-A

The F-11 chip set (code-named 'Fonz') was DEC's second microprocessor implementation of the PDP-11 architecture. It was used in the KDF11 CPUs. The main CPU was implemented in two chips (carried on a single DIP carrier).

Unlike the first microprocessor implementation (the LSI-11), the full F-11 chip set implemented the full PDP-11 architecture, including the optional KTF11-A memory management chip which implemented standard PDP-11 Memory Management, and the optional KEF11-A floating point chip which implemented the FP11-compatible floating point.

(The KEF11-A requires the KTF11-A, since the floating point registers are actually in the KTF11-A. The reason why is not known; although the KEF11-A is microcode, there are enough pins for both the data bus, and the microcode bus.)

There is also a double-width 6-chip carrier, the KEF11-B CIS chip, which implements the PDP-11 Commercial Instruction Set (CIS); not all KDF11 CPUs can hold this, though.

Chip versions

The data paths chip is the DC302, DEC part number 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, ALU, etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).

ODT limitations

The F-11 chip set includes microcode which provides 'front panel' functionality named 'ODT'; the ability to read and write to main memory, start the processor, etc. However, the original version of the KDF11-A only supported 18-bit addressing, and even though later versions supported 22-bit addressing, ODT in the KDF11's was always limited to 18-bit addressing: i.e. it is impossible to interact with memory above 256 Kbytes from ODT.

The later KDJ11 CPUs do not have this limitation.

See also

External links


v • d • e PDP-11 Computers and Peripherals
UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70
PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94

QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93

QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E

Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI

Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management

UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U

Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11

Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11

CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B

Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store

Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P

More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS

PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150   CTI PDP-11s - PRO-325 • PRO-350 • PRO-380

Clones: CM 1420 • SM 1420

Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences

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