Difference between revisions of "PDP-11/24"
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| − | + | [[Image:pdp11-24.jpg|250px|thumb|right|PDP-11/24 in BA11-A box]] | |
| − | + | The '''PDP-11/24''' was the last low-end [[UNIBUS]] [[PDP-11]] system; it used the [[KDF11-U CPU]]. Like the earlier [[PDP-11/44]], the -11/24 supported up to 4 Mbytes of [[main memory]], using the [[Extended UNIBUS]] between the [[CPU]] and memory; all devices were attached to a semi-separate (see below) UNIBUS. | |
| − | + | An optional [[UNIBUS map]] board, the [[KT24 UNIBUS map option|KT24]], provided a path between the UNIBUS and the EUB for access to all of memory for UNIBUS [[Direct Memory Access|DMA]] devices; without it, the UNIBUS [[address space]] was statically mapped across to the low 248 Kbytes of EUB main memory, using a cross-connection path on the [[Central Processing Unit|CPU]] board. If no KT24 was present, the CPU detected its absence, and turned on a set of drivers on the CPU card which gated the address from the UNIBUS through to the EUB. | |
| − | |||
| − | |||
| − | |||
| − | If no KT24 was present, the CPU detected its absence, and turned on a set of drivers which gated the | ||
==System bus structure== | ==System bus structure== | ||
| − | As mentioned, the -11/24 used an EUB for the bus between the main memory and the CPU, and the UNIBUS for the bus between the CPU and devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines. | + | As mentioned, the -11/24 used an EUB for the bus between the main memory and the CPU, and the UNIBUS for the bus between the CPU and devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines. (The lower address lines cannot be shared between the two busses, since the UNIBUS map provides arbitrary mapping from UNIBUS addresses to main memory addresses; so there are no lines which are guaranteed to have the same values, to allow them to be shared between the two busses.) |
Either the CPU, or the optional KT24, provided a path for addressing information to flow from the UNIBUS to the EUB, for DMA access to main memory by devices. | Either the CPU, or the optional KT24, provided a path for addressing information to flow from the UNIBUS to the EUB, for DMA access to main memory by devices. | ||
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===Implementation details=== | ===Implementation details=== | ||
| − | The -11/24 used a custom 9-slot [[backplane]] (part | + | The -11/24 used a custom 9-slot [[backplane]] ([[DEC part number]] 54-13817, assembly 70-16905); slot 1 was a custom slot for the KDF11-U CPU, slot 2 was likewise custom, and could hold either EUB memory or the KT24 UNIBUS map; slots 3-6 could hold either EUB memory or UNIBUS [[Small Peripheral Controller|SPC]] devices. Slots 7-8 were ordinary UNIBUS [[Modified UNIBUS Device|MUD]]/SPC slots, and slot 9 was an ordinary UNIBUS SPC/UNIBUS Out slot. |
| − | The EUB and UNIBUS address lines were kept totally separate in all the slots which supported the EUB (1-6); the 22-bit EUB address bus is carried on the EUB address lines (on [[DEC edge connector contact identification|connectors A-B]]), and the 18-bit UNIBUS addresses are carried on the SPC address pins (on connector E). | + | The EUB and UNIBUS address lines were kept totally separate in all the slots which supported the EUB (1-6); the 22-bit EUB address bus is carried on the EUB address lines (on [[DEC edge connector contact identification|connectors A-B]]), and the 18-bit UNIBUS addresses are carried on the SPC address pins (on connector E). |
The data lines were cross-connected between the EUB and SPC/UNIBUS. That is because the DEC EUB memory boards pick up the data lines on connector A, whereas UNIBUS SPC devices must get them on connector C - and the memory/SPC slots of the -11/24 backplane can hold either. | The data lines were cross-connected between the EUB and SPC/UNIBUS. That is because the DEC EUB memory boards pick up the data lines on connector A, whereas UNIBUS SPC devices must get them on connector C - and the memory/SPC slots of the -11/24 backplane can hold either. | ||
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| − | Any slot which can hold a device, but which does not have a device installed in it, must have a [[bus grant|grant]] continuity card such as a [[ | + | Any slot which can hold a device, but which does not have a device installed in it, must have a [[bus grant|grant]] continuity card such as a [[G727 grant continuity card|G727]] placed in it. |
| + | |||
| + | Note that slots 3-6 come pre-wired with [[Non-Processor Request and Grant|NPG]] [[jumper]]s (between pins CA1 and CB1, as is usual for SPC slots), and slots 7-8 do not; those slots will need either the jumper added, or a [[G7273 grant continuity card]] installed, if a non-DNA device is installed in them. (See Appendix C, 'PDP-11/24 Backplane Assignments', in the 'PDP-11/24 System Technical Manual', for details.) | ||
===Packaging=== | ===Packaging=== | ||
| − | The -11/24 came in two different cabinets, the 5-1/4 inch high [[BA11-L mounting box|BA11-L]] and the 10-1/2 inch [[BA11-A mounting box|BA11-A]] - the same mounting box as used in the -11/44. The backplane of the | + | The -11/24 came in two different cabinets, the 5-1/4 inch high [[BA11-L mounting box|BA11-L]] and the 10-1/2 inch [[BA11-A mounting box|BA11-A]] - the latter being the same mounting box as used in the -11/44. |
| + | |||
| + | The former is specified to use either the -UA (120VAC input) or -UB (240V) versions of the [[H777 Power Supply]] for the -11/24, to provide +/- 15 [[voltage|volt]] power for use by its [[EIA RS-232 serial line interface|RS232]] [[asynchronous serial line]]s. | ||
| + | |||
| + | The latter ('''''only''''') provides the 12V needed for the [[MS11-M MOS memory|MS11-M]] EUB memory - although the manual does not mention the use of this memory in the -11/24. The two memories which are mentioned - the [[MS11-L MOS memory|MS11-L]] (which can run on 15V) and [[MS11-P MOS memory|MS11-P]] (which only uses +5V) - should be able to use either mounting box variant (but see below for limits in the BA11-L). | ||
| + | |||
| + | The CPU backplane of the -11/44 uses unique [[Flexprint cable]]s for power, which go to special connections on [[bus bar]]s in the BA11-A's [[power supply]], though, not the standard [[DEC power distribution connectors]] used by the -11/24 backplane (as in the BA11-L mounting box). So, the -11/24 needs a special 'Power Distribution Board' (part # 54-13815) for the BA11-A, which mounts to the bus bars and provides the needed connectors. | ||
==Memory configuration limits== | ==Memory configuration limits== | ||
| − | The "PDP-11 UNIBUS Processor Handbook" (1985) says (pg. 4-10) that in the [[BA11-L mounting box|5.25" box]], "only one | + | The "PDP-11 UNIBUS Processor Handbook" (1985) says (pg. 4-10) that in the [[BA11-L mounting box|5.25" box]], "only one MS11-P memory module can be configured". The cause/source of that restriction is not given. |
| + | |||
| + | It can't be the backplane; i) the 5.25" and 10.5" (for which no limitation is stated) boxes use the same backplane, and ii) the 5.25" box can take more of the smaller MS11-L cards (albeit, again, limited - to three). The backplane does carry all 22 address lines to all EUB slots, and the CPU does drive all 22. So, it's likely that it's a power supply [[current]] issue. | ||
| + | |||
| + | The MS11-P only uses +5V, but there's nothing about limiting the number of other (ordinary) boards when an MS11-P is in use. The power supply specs show the BA11-L provides 32A of +5V and 4A of +5VBB; alas, the power consumption specs for the CPU and UNIBUS Map (which is basically necessary, for use of more than 256 Kbytes of memory) boards are not given. | ||
| − | + | However, the MS11-P uses up to 5A of +5V, and 3A of +5VBB; the MS11-L uses up to 2A of +5V, and 1.3A of +5VBB. The limited amount of +5VBB in the BA11-L does correspond to the limitations on the number of MS11-L and MS11-P boards. | |
| − | + | ==External links== | |
| − | + | * [http://www.bitsavers.org/pdf/dec/pdp11/1124/ PDP-11/24 documentation] | |
| + | ** [http://www.bitsavers.org/pdf/dec/pdp11/1124/EK-11024-TM-001_PDP11_24_System_Technical_Manual_Jun81.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-001) | ||
| + | ** [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_Rev_F_11-24_Engineering_Drawings_Mar84.pdf 11/24 Field Maintenance Print Set] (MP01018) | ||
| + | * [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) | ||
| + | * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Processor_Handbook_1981.pdf pdp11 processor handbook - pdp11/04/24/34A/44/70] | ||
| − | {{PDP-11}} | + | {{Nav PDP-11}} |
| − | [[Category:UNIBUS PDP-11s]] | + | [[Category: UNIBUS PDP-11s]] |
| + | [[Category: Extended UNIBUS]] | ||
Latest revision as of 22:37, 29 February 2024
The PDP-11/24 was the last low-end UNIBUS PDP-11 system; it used the KDF11-U CPU. Like the earlier PDP-11/44, the -11/24 supported up to 4 Mbytes of main memory, using the Extended UNIBUS between the CPU and memory; all devices were attached to a semi-separate (see below) UNIBUS.
An optional UNIBUS map board, the KT24, provided a path between the UNIBUS and the EUB for access to all of memory for UNIBUS DMA devices; without it, the UNIBUS address space was statically mapped across to the low 248 Kbytes of EUB main memory, using a cross-connection path on the CPU board. If no KT24 was present, the CPU detected its absence, and turned on a set of drivers on the CPU card which gated the address from the UNIBUS through to the EUB.
Contents
System bus structure
As mentioned, the -11/24 used an EUB for the bus between the main memory and the CPU, and the UNIBUS for the bus between the CPU and devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines. (The lower address lines cannot be shared between the two busses, since the UNIBUS map provides arbitrary mapping from UNIBUS addresses to main memory addresses; so there are no lines which are guaranteed to have the same values, to allow them to be shared between the two busses.)
Either the CPU, or the optional KT24, provided a path for addressing information to flow from the UNIBUS to the EUB, for DMA access to main memory by devices.
The top 256 Kbytes of the CPU's address space were devoted to the UNIBUS; the top 8 Kbytes of that were, as usual, the peripheral page.
Implementation details
The -11/24 used a custom 9-slot backplane (DEC part number 54-13817, assembly 70-16905); slot 1 was a custom slot for the KDF11-U CPU, slot 2 was likewise custom, and could hold either EUB memory or the KT24 UNIBUS map; slots 3-6 could hold either EUB memory or UNIBUS SPC devices. Slots 7-8 were ordinary UNIBUS MUD/SPC slots, and slot 9 was an ordinary UNIBUS SPC/UNIBUS Out slot.
The EUB and UNIBUS address lines were kept totally separate in all the slots which supported the EUB (1-6); the 22-bit EUB address bus is carried on the EUB address lines (on connectors A-B), and the 18-bit UNIBUS addresses are carried on the SPC address pins (on connector E).
The data lines were cross-connected between the EUB and SPC/UNIBUS. That is because the DEC EUB memory boards pick up the data lines on connector A, whereas UNIBUS SPC devices must get them on connector C - and the memory/SPC slots of the -11/24 backplane can hold either.
In fact, the CPU board connects to the data bus on the C connector, i.e. the UNIBUS SPC pins. The KT24, contrastingly, uses connector A (the MUD pins) for access to the data bus. The reason for the difference is not known - perhaps board layout issues?
With no KT24, a standard EUB memory can go in slot 2; that slot is special, though (i.e. wired differently from slots 3-6). The KT24 needs not only the UNIBUS lines and EUB address lines (to map from one to the other), it also has some special interconnects with the CPU, (e.g. the 'UNIBUS adapter present' line). Bus grant lines also bypass slot 2; hence the limitation to the KT24 or memory.
Layout
Board locations are:
| Connector | ||||||
|---|---|---|---|---|---|---|
| Slot | A | B | C | D | E | F |
| 1 | M7133 CPU | |||||
| 2 | M7134 UBA or EUB memory | |||||
| 3 | EUB memory or SPC device | |||||
| 4 | EUB memory or SPC device | |||||
| 5 | EUB memory or SPC device | |||||
| 6 | EUB memory or SPC device | |||||
| 7 | MUD device | |||||
| 8 | MUD device | |||||
| 9 | UNIBUS Out | SPC | ||||
Any slot which can hold a device, but which does not have a device installed in it, must have a grant continuity card such as a G727 placed in it.
Note that slots 3-6 come pre-wired with NPG jumpers (between pins CA1 and CB1, as is usual for SPC slots), and slots 7-8 do not; those slots will need either the jumper added, or a G7273 grant continuity card installed, if a non-DNA device is installed in them. (See Appendix C, 'PDP-11/24 Backplane Assignments', in the 'PDP-11/24 System Technical Manual', for details.)
Packaging
The -11/24 came in two different cabinets, the 5-1/4 inch high BA11-L and the 10-1/2 inch BA11-A - the latter being the same mounting box as used in the -11/44.
The former is specified to use either the -UA (120VAC input) or -UB (240V) versions of the H777 Power Supply for the -11/24, to provide +/- 15 volt power for use by its RS232 asynchronous serial lines.
The latter (only) provides the 12V needed for the MS11-M EUB memory - although the manual does not mention the use of this memory in the -11/24. The two memories which are mentioned - the MS11-L (which can run on 15V) and MS11-P (which only uses +5V) - should be able to use either mounting box variant (but see below for limits in the BA11-L).
The CPU backplane of the -11/44 uses unique Flexprint cables for power, which go to special connections on bus bars in the BA11-A's power supply, though, not the standard DEC power distribution connectors used by the -11/24 backplane (as in the BA11-L mounting box). So, the -11/24 needs a special 'Power Distribution Board' (part # 54-13815) for the BA11-A, which mounts to the bus bars and provides the needed connectors.
Memory configuration limits
The "PDP-11 UNIBUS Processor Handbook" (1985) says (pg. 4-10) that in the 5.25" box, "only one MS11-P memory module can be configured". The cause/source of that restriction is not given.
It can't be the backplane; i) the 5.25" and 10.5" (for which no limitation is stated) boxes use the same backplane, and ii) the 5.25" box can take more of the smaller MS11-L cards (albeit, again, limited - to three). The backplane does carry all 22 address lines to all EUB slots, and the CPU does drive all 22. So, it's likely that it's a power supply current issue.
The MS11-P only uses +5V, but there's nothing about limiting the number of other (ordinary) boards when an MS11-P is in use. The power supply specs show the BA11-L provides 32A of +5V and 4A of +5VBB; alas, the power consumption specs for the CPU and UNIBUS Map (which is basically necessary, for use of more than 256 Kbytes of memory) boards are not given.
However, the MS11-P uses up to 5A of +5V, and 3A of +5VBB; the MS11-L uses up to 2A of +5V, and 1.3A of +5VBB. The limited amount of +5VBB in the BA11-L does correspond to the limitations on the number of MS11-L and MS11-P boards.
External links
- PDP-11/24 documentation
- PDP-11/24 System Technical Manual (EK-11024-TM-001)
- 11/24 Field Maintenance Print Set (MP01018)
- PDP-11/24 System Technical Manual (EK-11024-TM-003)
- pdp11 processor handbook - pdp11/04/24/34A/44/70
| v • d • e PDP-11 Computers and Peripherals |
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| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
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