Difference between revisions of "FP11-B Floating-Point Processor"
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Revision as of 03:18, 25 April 2016
The FP11-B was a FPP used in the PDP-11/45 and PDP-11/70 computers (KB11-A and KB11-B CPU variants thereof, respectively); it operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time.
It supported short (32 bit) and long (64 bit) floating point numbers; both forms used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining bits were the fractional part. A state bit controlled whether the FP11-B operated in short or long mode.
The FP11-B contained 6 internal registers, each capable of holding either a short or long floating point value.
Implementation
The FP11-B runs entirely asynchronously to the main CPU; it used a clock which is not synchronized to the basic CPU's clock. It plugged into special pre-wired slots in the CPU's backplane, and included the following boards:
- M8112 ROM and ROM Control
- M8113 Exponent and Data Path
- M8114 Fraction Data Path - High Order
- M8115 Fraction Data Path - Low Order
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Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |