KT11-B Technical Manual

As a Special Systems Option, the KT11-B does not have the usual DEC Technical Manual. This page attempts to provide at least the high-level portions of such a manual.

Prints

The Engineering Drawings for the KT11-B (7605071) include the following logic prints:

Number	Page Count	Content
2	2	Address Bus and Control Logic
3	1	State Control Logic
4	1	SP Input Mux
5	2	Associative Memory Control
6	1	Scratch Pad and State Control Logic
7	3	Data Bus and Control Logic
8	1	Keys and Associative Memory
9	1	XP Option for KT11 Associative Memory Control
10	1	PGM Register
11	1	PGC Register
12	1	Timing Logic
13	1	Buffered Signals and Main Logic
14	1	Extended Associative Memory
15	1	KA11 to KT11 Interface
17	1	KT11-B Bus Connectors

Drawing Conventions

The drawings are somewhat easier to understand if the conventions used in the drawings are understood. Although no document lists them, they can be ascertained by study of the drawings.

Signal Names

Signal names in this drawing set usually start with 'Dxx', where 'xx' is the drawing number (given in the table above). Inverted (asserted low) signals are shown as '-XXX'. In signal names of the form 'XXX (yy)', 'yy' is a bit number (in standard PDP-11 order) in a register or bus.

The following specific signal names have the meaning given:

• Signals of the form 'x.y' are states, with 'x' being the major state, and 'y' being the minor state.

Common Circuits

This circuit (first used in the KA11) is seen in several places in the KT11-B. It is almost always seen as an array of identical circuits, since it provides a 3-input multiplexor with latching capability, and it is used on data paths (usually 16 bits wide).

The latch is cleared by de-asserting the 'Latch' input; data from any of the three inputs (A, B, C) may then be selected for output, and potentially storage, by asserting the matching 'Gate' input. Asserting 'Latch' then stores the current output of the mux.

States

The KT11-B has a state composed of two parts, the 'X' or major part, and the 'Y' or minor part; the progression of this through the various states is the major control mechanism in the KT11-B.

The X state counter is on print 12; it is composed of a 2-bit counter composed of a pair of D flops, with 4 AND gates with inverting inputs to create individual major state outputs, signals 'XSRx' (x = 0-3).

The Y state counter is an M826 Flip Chip, showm on print 8; its outputs are signals 'YSRx' (x = 0, 1 ,3, 7, 15, 14, 12, 8). (The odd sequence of minor state numbers, and the fact that they are not in numerical order, is confusing, but since that's what's on the prints, that nomenclature has to be used.)

The two groups of signals are combined into signals which indicate that the KT11-B is in that state, for each individual major/minor state, by NAND gates shown on drawing 12; inverters then provide non-inverted forms of each.

Construction

The KT11-B is constructed out of a large number of smaller Flip Chips. The card type usage counts are:

Type	Function	Count	Comment
M111	16 x Inverters	10	9?
M112	10 x 2-input NOR	5	4? (but there's a '117' could be 112)
M116	6 x 4-input NOR	10
M133	10 x 2-input NAND	24
M135	8 x 3-input NAND	6
M139	3 x 8-input NAND	1
M167	Magnitude comparator	1
M203	8 x R/S flip flops	1
M206	6 x D flip flops	1
M207	6 x J/K flip flops	1
M225	Scratchpad memory	1	2?
M240	R/S flip flop	1
M244	Mutiplexor latch	6
M259	Associative memory	4	10/12?
M602	2 x Pulse amplifier	1
M611	14 x Power inverter	3
M627	6 x NAND amplifier	7
M721	UNIBUS transceiver	4
M783	12 x UNIBUS NAND transmitters	6
M784	16 x UNIBUS inverter receivers	2
M826	Clock/shift register	1

(The counts are from the list in the "KT11-B Option Description" document; they have been cross-checked against the 'Module Utilization' sheet from the KT11-B Engineering Drawings, and there are still some variances to be sorted out.)