PDP-11 architecture

The PDP-11 is a family of 16-bit minicomputer designed by DEC, in production from 1970-1990. Although the basic address space was 16 bits, most models could hold more memory than that, although only a limited subset was visible to the program at any time.

It had 8 general purpose registers; the operand coding, which was applied regularly across essentially the entire instruction set, allowed it to provide a two-address instruction architecture, not simple load-store architecture like its predecessor, the 12-bit PDP-8.

One of the registers was dedicated to be the Program Counter, and one was more or less dedicated to be the Stack Pointer. (Other registers can be used as stack pointers, but the hardware uses this one for interrupts, etc.)

These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit words.

The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size. This was an important consideration both in the PDP-11's early life, when small and expensive core memory was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.

Most instructions come in both byte and word forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).

Extensions

The first PDP-11 (the PDP-11/20) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware floating point. The next model, the PDP-11/45, added both of these (the latter as an option), although the follow-on low-cost machines, the PDP-11/05 and PDP-11/04, again did not have either.

Later machines tended to include the former group - although on some early mid-range machines such as the PDP-11/40 and PDP-11/03, they were only an option. Floating point was also added to the later machines (although only as an option, until relatively late in the line).

Late in the PDP-11 family's lifetime, a PDP-11 Commercial Instruction Set was defined, and made available as an option in some of the later machines.

Floating point

Two forms of floating point were added: a simplified form, FIS floating point, with only the 4 basic operations, using 32-bit variables, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), FP11 floating point.

The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the PDP-11/45 and variants thereof (the PDP-11/50 and PDP-11/55), the PDP-11/70, PDP-11/34, PDP-11/44 and PDP-11/23; it was standard in the KDJ11-B and KDJ11-E (although in all these machines an optional FPJ11 floating point accelerator greatly improved the floating point throughput).

Memory management

After a few disparate custom add-on units to provide memory management in the PDP-11/20, memory management became standardized with the PDP-11/45 (in which it was an option); most later machines supported it. A simplified version was supported in the -11/40 and -11/23 (as an option), and in the -11/34 (standard).

Operands

The PDP-11 supported both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode.

As noted above, this operand form provided a large variety of operand types, including stack push and pop, literals, etc. This provides the basic instruction group with great flexibility, especially the double-operand instructions (MOV, ADD, etc).

A few instructions (mostly those which were added to the instruction repertoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. if not already in a register, that operand must be pre-loaded into one by another instruction).

Addressing modes

The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes:

Mode	Name	Symbolic	Description
0	Register	R	(R) is the operand
1	Register deferred	(R)	(R) contains address of operand
2	Auto-increment	(R)+	(R) is the address; (R) is incremented by 1 or 2, in case of byte or word instructions.
3	Auto-increment deferred	@(R)+	(R) is the address of the address; (R) is incremented by 2
4	Auto-decrement	(R)-	(R) is decremented by 1 or 2, in case of byte or word instructions; R is address.
5	Auto-decrement deferred	@(R)-	(R) is decremented by two; (R) is the address of the address.
6	Index	X(R)	(R) + X is the address.
7	Index deferred	@X(R)	(R) + X is the address of the address

Auto-increment and auto-decrement allow any register to be used as a stack pointer; the hardware enforces the use of R6 as the stack pointer for some operations, though (e.g. subroutine call and return), so it is un-common for another register to be used for this. The use of auto-increment mode with the program counter provides immediate (literal) operands, though.

Instruction set

The instruction set provided a number of double-operand instructions:

• MOV
• ADD
• SUB
• BIT (bit test)
• BIS (bit set)
• BIC (bit clear)

(as noted, ADD and SUB are only available in word mode), and many single-operand instructions:

• CLR
• TST (compare with 0)
• INC
• DEC
• NEG
• COM (complement)
• ASR (arithmetic shift right)
• ASL
• ROR (rotate right)
• ROL
• SWAB (swap bytes)
• ADC (add carry)
• SBC

Condition codes and conditional branches

The instruction set provided a plethora of branches, although all branches are limited to a range of 127 words before or after the current instruction; a limit which is not onerous in practise. All the conditional branches depend on a prior instruction to set 4 condition codes (stored in the Processor Status Word):

• Z - Zero
• N - Negative (i.e. high bit set)
• C - Carry
• V - Overflow

Conditional branches:

• BR (un-conditional)
• BNE (non-zero)
• BEQ (zero)
• BMI (negative)
• BPL (positive)
• BVC (overflow clear)
• BVS (overflow)
• BCS (carry)
• BCC (no carry)

Signed branches:

• BGE (greater than or equal to 0)
• BGT
• BLE
• BLT

Unsigned branches:

• BHIS (higher than, or the same)
• BHI
• BLOS
• BLO

Miscellaneous

Other flow of control instructions (both JMP and JSR) can transfer to any location in the address space):

• JMP
• JSR - subroutine call
• RTS - subroutine return

A variety of other instructions (e.g. to trap to the operating system, halt the CPU, etc) also exist.

Added later

The PDP-11/45 added a few miscellaneous instructions:

• SOB (decrement and conditionally branch)
• XOR (word only, and also only provides a register number for one operand)
• SXT (sign extend, word only)
• MARK (subroutine argument setup)
• RTT (return from interrupt while inhibiting 'trace' trap)
• SPL (set CPU priority level)

All of these, with the exception of SPL, appeared in all later models except the -11/05 and -11/04.

Various later models added various instructions for Processor Status Word access, maintenance, etc.