PDP-11/45

A PDP11-45

PDP-11/45
Manufacturer:	Digital Equipment Corporation
Year Introduced:	June 1972
Word Size:	16 bit
Physical Address Size:	18 bit
Virtual Address Size:	16 bit
Bus Architecture:	UNIBUS/FastBus

The PDP-11/45 was a fast UNIBUS PDP-11 system using the KB11-A (early units, prior to 1976) or KB11-D (later) CPU, a high-performance CPU implemented in SSI Schottky TTL logic. (The difference between the two was whether they worked with the FP11-B or FP11-C FPP.)

The PDP-11/50 and PDP-11/55 were systems which used the exact same processor, but were configured with high-speed MOS or bipolar memory, respectively, on a special bus which was part of the CPU's backplane.

Optionally, the machine could be configured with a KT11-C memory management unit; the FP11 floating-point processor was also optional.

The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.

KB11-A CPU

The KB11-A board set included:

• M8100 Data and Address Paths
• M8101 General Register and Control
• M8102 Instruction Register and Decode
• M8103 ROM and ROM Control
• M8104 Processor Data and UNIBUS Registers
• M8105 Timing and Miscellaneous Control
• M8106 UNIBUS and Console Control
• M8109 Timing Generator

In addition, the CPU includes either:

• M8116 Segmentation Jumper Board

used when the KT11-C memory management unit is not present, or:

• M8107 Segmentation Address Paths
• M8108 Segmentation Status Registers

which comprise the KT11-C.

KB11-D CPU

The KB11-D board set included many of the same boards as the KB11-A, with the following differences:

• The M8102 Instruction Register and Decode was replaced with the M8132
• The M8103 ROM and ROM Control was replaced with the M8123
• The M8106 UNIBUS and Console Control was replaced with the M8119

When the KT11-C memory management unit (termed the KT11-CD in this CPU) was present, the M8108 Segmentation Status Registers board of the KB11-A was replaced with the M8108-YA variant.

hampage.hu

Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.

The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.

The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11D) used the modified CPU of the PDP-11/70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.

Documentation

• EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual

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