PDP-11/45

A PDP-11/45

PDP-11/45
Manufacturer:	DEC
Architecture:	PDP-11
Year Introduced:	June 1972
Form Factor:	minicomputer
Word Size:	16 bit
Design Type:	microcoded
Physical Address Size:	18 bit
Virtual Address Size:	16 bit
Bus Architecture:	UNIBUS/FastBus

The PDP-11/45 was the early fast UNIBUS PDP-11 system, using the KB11-A CPU (early units, prior to 1976) or KB11-D CPU (later units) high-performance CPUs, implemented in SSI Schottky TTL logic.

The difference between the two CPUs was whether they worked with the FP11-B or FP11-C FPP. The FP11 Floating-Point Processor was optional, as was the KT11-C Memory Management Unit (the first implementation of the full PDP-11 Memory Management).

The PDP-11/50 and PDP-11/55 were systems which used the exact same processor, but were sold configured with special high-speed MOS or bipolar memory, respectively.

The machine's 18-bit UNIBUS, allowing it to have up to 256Kbytes of main memory. Later non-DEC products such as the Able ENABLE allowed use of up to 4Mbytes, via the Extended UNIBUS.

High-speed memory

The high-speed memory was dual-ported, to a special high-speed bus to the CPU (called the Fastbus), which was part of the CPU's backplane, and also to a second UNIBUS.

That UNIBUS could either be connected to a second PDP-11 (creating a multi-processor PDP-11 system), or the -11/45's main UNIBUS, so that DMA devices on that UNIBUS could do I/O to that memory.

The high-speed memory could be configured in two semi-independent banks, each with its own M8110 (later M8120) Semiconductor Memory Control module.

hampage.hu

Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.

The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.

The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the PDP-11/70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.

Documentation

• EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual

Gallery