J-11 chip set: Difference between revisions

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Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].
Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].
==External link==
* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]


{{PDP-11}}
{{PDP-11}}


[[Category: PDP-11 Processors]]
[[Category: PDP-11 Processors]]

Revision as of 15:58, 15 July 2018

J-11

The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, used in both the KDJ11 CPUs, and a variety of peripherals. It was implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.

It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating point support (using microcode), it can operate with an FPJ11 floating point accelerator chip.

Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.

External link