Difference between revisions of "J-11 chip set"
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The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier. | The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier. | ||
| − | It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11 | + | It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an optional [[FPJ11 floating point accelerator]] [[integrated circuit|chip]] for higher performance. |
Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]]. | Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]]. | ||
Revision as of 21:31, 5 January 2020
The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, used in both the KDJ11 CPUs, and a variety of peripherals. It was implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.
It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating point support (using microcode), it can operate with an optional FPJ11 floating point accelerator chip for higher performance.
Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.
External link
| v • d • e PDP-11 Computers and Peripherals |
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| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
