MSV11-J memory module

The MSV11-J (M8637) is a QBUS/PMI DRAM main memory card. As a PMI card, it uses the CD interconnect; it can therefore only be plugged into a Q/CD backplane. NOTE: Plugging an MSV11-J card into a regular Q/Q backplane will damage the MSV11-J.

It has ECC which automagically corrects single-bit errors (at a slight penalty in response time when an error occurs), and detects double-bit errors. It holds 2 Mbytes when fully populated with 256Kx1 DRAM chips, or 1 Mbyte when half-populated (the only partially-filled configuration allowed). It supports block mode on both the QBUS and PMI.

Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable CPU, such as the KDJ11-B. In systems such as the PDP-11/83, where the primary I/O bus is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the PDP-11/84, PMI is used for communication with both the CPU and the KTJ11-B UNIBUS adapter.

The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold words at even word locations, the other for those in odd; the banks are thus interleaved. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.

On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For diagnostic purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.

Four versions exist:

• MSV11-JB, 1 Mbyte
• MSV11-JC, 2 Mbyte
• MSV11-JD, 1 Mbyte
• MSV11-JE, 2 Mbyte

The -JB and -JC are earlier versions, which contain an error which prevents them working properly as QBUS memories (i.e. in the PDP-11/83); they are only usable in the PDP-11/84.

Register

Each board has a single control register, which can be configured in the range 172100-172136.

In the register contents (below), all the bits can be read and written by software; most are cleared by power up and bus INIT, except the multi-function (address/CRC) bits. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the hardware in italics.

Uncorrected error	Extended address	Set inhibit mode	Reserved	Multi-function							Single error	Inhibit mode pointer	Diagnostic mode	Disable correction	Error indication
15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00

The multi-function field contents depend on what is being done; it is used to hold the address of an error; and also to read, and in diagnostic mode write, the ECC bits (called 'syndrome' when read, and 'check' when written).

When it holds the low address (the low/high choice is controlled by bit 14), it holds address bits 11 through 17; when it holds the high address, bits 21 through 18, and in register bit 9, address bit 1 (to tell which bank the error was in) - bits 11-10 are unused.

When it holds the ECC bits, this is the mapping from CSR bits to ECC bits:

CSR bit	Syndrome	Check
040	CBx	Snx
0100	CB0	Sn0
0200	CB1	Sn1
0400	CB2	Sn2
01000	CB4	Sn4
02000	CB8	Sn8

Technical information

As far as is known, there are no engineering drawings extant for the MSV11-J. However, some technical information has been gathered on the board, and it is made available here.

To start with, unlike other DEC boards, this board does not contain the Exx identification numbers for chips on the board. The following scheme has therefore been devised, to identify the DRAM chips for the bit to chip table below.

The DRAM chips are organized into four blocks; block 0 and 2 hold words in the even-numbered word bank, and 1 and 3 hold those in the odd-numbered word bank. With the component side of the board facing, and the metal insertion handle at the top, the pair of low-address blocks (0 and 1) are at the top of the card, and the optional pair of high-address blocks (2 and 3) are at the bottom.

The low half of the even-numbered word bank is on the right side (denoted with an 'R'), and the low half of the odd bank on the left ('L'). (The high half has the sides reversed.) There are three columns on each side (denoted '0'-'2', with the '0' column at the left of each group). Each column contains 17 chips (denoted '0'-'16', with '0' at the top).

Chips are identified as SCRr, where 'S' is the side ('L' or 'R'), C is the column, and 'Rr' is the row. Note that not all the chips in this area are DRAM; for example, in block 1, chips L17, L27, L211, and L213 and up, are not DRAM.

Bit	Block 0	Block 1	Block 2	Block 3
01	R05	L02
02	R14	L12
04	R24	L22
10	R04	L03
20	R13	L13
40	R23	L23
100	R03	L04
200	R22	L14
400	R12	L24
1000	R02	L05
2000	R21	L15
4000	R11	L25
10000	R01	L06
20000	R20	L16
40000	R10	L26
100000	R00	L07
CBx	R25	L21
CB0	R27	L00
CB1	R26	L10
CB2	R16	L20
CB4	R06	L01
CB8	R15	L11

Markings

On the board

M8637
Side 1
L1
50-15672-01 C1
Ga6618
2644711
2 MB Q,P-BUS MOS MEM
LPWR
TPB
D.V0

On the metal frame

P/N 1213113
M8637
EC

ASICs on board are 21-24404-01 and 21-22772-01