PDP-11 architecture

The PDP-11 is a family of 16-bit minicomputer designed by DEC, in production from 1970-1990.

It had 8 registers, of which one dedicated to be the program counter, and one was more or less dedicated to be the stack pointer. These registers, along with a variety of register-based addressing modes, allowed it to provide a two-address instruction architecture, not simple load-store like its predecessor, the 12-bit PDP-8.

Early machines were limited to one-bit shift operations, and did not have hardware integer multiplication or division; or any hardware floating point. Later machines tended to include the former (on some early mid-range machines such as the PDP-11/40 and PDP-11/03, they were an option).

Floating point

Two forms of floating point were later added: a simplified form (only the 4 basic operations, with 32-bit variables), and full-blown floating point (32-bit and 64-bit formats, many operations).

The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the PDP-11/45 and variants thereof, the PDP-11/70, [PDP-11/34]], PDP-11/44 and PDP-11/23; it was standard in the PDP-11/73, KDJ11-B and KDJ11-B (although in all these machines an optional FPJ11 Floating Point Accelerator greatly improved the floating point throughput).

Memory management

After a few disparate custom add-on units to provide memory management in the PDP-11/20, memory management became standardized with the PDP-11/45 (in which it was an option); most later machines supported it. A simplified version was supported in the -11/40 and -11/23 (as an option), and in the -11/34.

Operands

The PDP-11 supports both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode.

This provides the basic instruction group (MOV, ADD, etc) with great flexibiilty, and reduces the code size; an important consideration in the PDP-11's early life, when small and expensive core memory was the standard main memory.

A few instructions (mostly those which were added to the instruction repetoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. that operand must be pre-loaded by another instruction).

Addressing modes

The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes:

Mode	Name	Symbolic	Description
0	Register	R	(R) is the operand
1	Register deferred	(R)	(R) contains address of operand
2	Auto-increment	(R)+	(R) is the address; (R) is incremented by 1 or 2, in case of byte or word instructions.
3	Auto-increment deferred	@(R)+	(R) is the address of the address; (R) is incremented by 2
4	Auto-decrement	(R)-	(R) is decremented by 1 or 2, in case of byte or word instructions; R is address.
5	Auto-decrement deferred	@(R)-	(R) is decremented by two; (R) is the address of the address.
6	Index	X(R)	(R) + X is the address.
7	Index deferred	@X(R)	(R) + X is the address of the address