PDP-11/45
| PDP-11/45 | |
| Manufacturer: | DEC |
|---|---|
| Architecture: | PDP-11 |
| Year Introduced: | June 1972 |
| Form Factor: | minicomputer |
| Word Size: | 16 bit |
| Design Type: | microcoded |
| Physical Address Size: | 18 bit |
| Virtual Address Size: | 16 bit |
| Bus Architecture: | UNIBUS/FastBus |
The PDP-11/45 was the early fast UNIBUS PDP-11 system, using the KB11-A CPU (early units, prior to 1976) or KB11-D CPU (later units), high-performance CPUs implemented in SSI Schottky TTL logic.
(The difference between the two was whether they worked with the FP11-B or FP11-C FPP.)
The PDP-11/50 and PDP-11/55 were systems which used the exact same processor, but were configured with high-speed MOS or bipolar memory, respectively, on a special bus which was part of the CPU's backplane.
Optionally, the machine could be configured with a KT11-C Memory Management Unit; the FP11 Floating-Point Processor was also optional.
The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.
hampage.hu
Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.
The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.
The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the PDP-11/70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
Documentation
Gallery
| v • d • e PDP-11 Computers and Peripherals |
|---|
| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
