MSV11-J memory module

The MSV11-J (M8637) is a QBUS/PMI DRAM main memory card. As a PMI card, it uses the CD interconnect; it can therefore only be plugged into a Q/CD backplane. NOTE: Plugging an MSV11-J card into a regular Q/Q backplane will damage the MSV11-J.

It has ECC which automagically corrects single-bit errors (at a slight penalty in response time), and detects double-bit errors. It holds up to 2 Mbyes when fully populated with 256Kx1 DRAM chips, or 1 Mbyte when half-populated (the only partially-filled configuration supported). It supports block mode on both the QBUS and PMI.

Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable CPU, such as the KDJ11-B. In systems such as the PDP-11/83, where the primary I/O bus is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the PDP-11/84, the PMI is used for communication with both the CPU and the KTJ11-B UNIBUS adapter.

The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold words at even locations, the other for those in odd. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.

On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the memory is cleared, to prevent spurious ECC errors. For diagnostic purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.

Four versions exist:

• MSV11-JB, 1 Mbyte
• MSV11-JC, 2 Mbyte
• MSV11-JD, 1 Mbyte
• MSV11-JE, 2 Mbyte

The -JB and -JC are earlier versions which contain an error which prevents them working properly as QBUS memories (i.e. in the PDP-11/83); they are only usable in the PDP-11/84.

Technical information

As far as is known, there are no engineering drawings extant for the MSV11-J. However, some technical information has been gathered on the board, and it is made available here.

Unlike other DEC boards, this board does not contain the Exx identification numbers for chips on the board. The following scheme has therefore been devised, to idenify the DRAM chips in the bit to chip table below.

The DRAM chips are organized into four blocks; block 0 and 2 hold words in the even word-number bank, and 1 and 3 hold those in the odd word-number bank. With the component side of the board facing, and the metal insertion handle at the top, the pair of low-address blocks (0 and 1) are at the top of the card, and the optional pair of high-address blocks (2 and 3) are at the bottom.

The even word-numbered bank is on the right side (denoted with an 'R'), and the odd bank on the left ('L'). There are three columns on each side (denoted '0'-'2', with the '0' column at the left of each group). Each column contains 17 chips (denoted '0'-'16', with '0' at the top). Chips are identified as SCRr, where 'S' is the side ('L' or 'R'), C is tyhe column, and 'Rr' is the row.

Bit	Block 0	Block 1	Block 2	Block 3
01	R05
02	R14
04	R24
10	R04
20	R13
40	R23
100	R03
200	R22
400	R12
1000	R02
2000	R21
4000	R11
10000	R01
20000	R20
40000	R10
100000	R00
CBx	R25
CB0	R27
CB1	R26
CB2	R06 or R16
CB4	R06 or R16
CB8	R15

Note that not all the chips in this area are DRAM; for example, in block 1, L17, L27, L211, and L213 and up are not DRAM.

Markings

On the board

M8637
Side 1
L1
50-15672-01 C1
Ga6618
2644711
2 MB Q,P-BUS MOS MEM
LPWR
TPB
D.V0

On the metal frame

P/N 1213113
M8637
EC

ASICs on board are 21-24404-01 and 21-22772-01