PDP-11/74

The PDP-11/74 was an experimental (it never went into production) tightly-coupled symmetric multi-processor version of the PDP-11/70 from DEC; it could hold from two to four CPUs.

It used a multi-port memory version of the MK11 memory system, the MKA11. Some devices, such as disks and magnetic tape drives, could be shared between two of the CPUs, using the multi-port capabilities of many MASSBUS devices; other devices (e.g. UNIBUS devices) could not be shared (other than via software, or use of a UNIBUS switch).

The CPU was the KB11-E CPU, a modified version of the KB11-C CPU of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private bus, allowed one CPU to interrupt or bootstrap another CPU. A multi-ported high-resolution 'Time of Day' clock was also provided. Also, the ASRB instruction implementation was modified to be atomic, for use in synchronization between CPUs.

There was also a planned Commercial Instruction Set processor, the CISP.

A significant run of prototypes were produced, and the RSX-11 operating system was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly the concern was that with its very high I/O bandwidth, it would compete with the new VAX-11/780, but this appears to be a canard; concern about its commercial viability was apparently the cause), and never appeared as a product.

External links

• PDP-11 Multiprocessor FAQ