T-11 chip

T-11 chip

The T-11 chip (formally the DCT11-AA, although most DEC documentation used 'T-11') was a microprocessor implementation of the PDP-11 architecture. It was primarily intended for use in embedded systems, but was also used in the KXT11 QBUS CPU boards. Volume production commenced in early 1982.

The T-11 implemented a subset of the PDP-11 architecture; it had neither memory management, nor floating point, and it omitted the little-used MARK instruction.

It was a single 40-pin DIP NMOS chip. It produced all the control outputs needed to directly drive DRAM main memory chips; 4K, 16K and 64K parts were all supported. It could also perform memory refresh of the DRAM. A configuration register, loaded at power-on, supported both 8-bit and 16-bit wide busses (along with other options). It needed +5V power only, and all of its signals were TTL-compatible.

Chip versions

There are three versions: two from DEC, DEC part number 21-17311-01, which operates at a maximum clock frequency of 7.5 MHz, and the 21-17311-02 which operates at a maximum frequency of 10 MHz; and the 21-17311-00 from a second source, Synertek, also a 7.5 MHz part. All versions are marked "310ES".

See also

• Another T-11

Further reading

• Using the Falcon SBC-11/21 in a Standalone Environment, MicroNote #109
• MUL, DIV, and ASH Instruction for the Falcon SBC-l1/21, MicroNote #110

External links

• μ/T-11 User's Guide
• T-11 Engineering Specification
• DEC Semiconductor Databook, Volume 1, pp. 361-411