Difference between revisions of "T-11 chip"
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[[Image:0DCT11.jpg|250px|thumb|right|T-11 chip]] | [[Image:0DCT11.jpg|250px|thumb|right|T-11 chip]] | ||
| − | The '''T-11 chip''' (formally the '''DCT11''', although [[Digital Equipment Corporation|DEC]] documentation | + | The '''T-11 chip''' (formally the '''DCT11-AA''', although most [[Digital Equipment Corporation|DEC]] documentation used 'T-11') was a [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was primarily intended for use in [[embedded system]]s, but was also used in the [[KXT11]] [[QBUS]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]]. Volume production commenced in early 1982. |
| − | The T-11 | + | The T-11 implemented a subset of the PDP-11 architecture; it had neither [[memory management]], nor [[floating point]], and it omitted the little-used MARK [[instruction]]. |
| − | It was a 40-pin [[Dual Inline Package|DIP]] [[NMOS]] chip. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses. It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible. | + | It was a single 40-pin [[Dual Inline Package|DIP]] [[NMOS]] [[integrated circuit|chip]]. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses (along with other options). It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible. |
==Chip versions== | ==Chip versions== | ||
There are three versions: two from DEC, [[DEC part number]] 21-17311-01, which operates at a maximum [[clock]] frequency of 7.5 MHz, and the 21-17311-02 which operates at a maximum frequency of 10 MHz; and the 21-17311-00 from a second source, Synertek, also a 7.5 MHz part. All versions are marked "310ES". | There are three versions: two from DEC, [[DEC part number]] 21-17311-01, which operates at a maximum [[clock]] frequency of 7.5 MHz, and the 21-17311-02 which operates at a maximum frequency of 10 MHz; and the 21-17311-00 from a second source, Synertek, also a 7.5 MHz part. All versions are marked "310ES". | ||
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| + | {{semi-stub}} | ||
==External links== | ==External links== | ||
Revision as of 12:15, 29 March 2021
The T-11 chip (formally the DCT11-AA, although most DEC documentation used 'T-11') was a microprocessor implementation of the PDP-11 architecture. It was primarily intended for use in embedded systems, but was also used in the KXT11 QBUS CPU boards. Volume production commenced in early 1982.
The T-11 implemented a subset of the PDP-11 architecture; it had neither memory management, nor floating point, and it omitted the little-used MARK instruction.
It was a single 40-pin DIP NMOS chip. It produced all the control outputs needed to directly drive DRAM main memory chips; 4K, 16K and 64K parts were all supported. It could also perform refresh of the DRAM. A configuration register, loaded at power-on, supported both 8-bit and 16-bit wide busses (along with other options). It needed +5V power only, and all of its signals were TTL-compatible.
Chip versions
There are three versions: two from DEC, DEC part number 21-17311-01, which operates at a maximum clock frequency of 7.5 MHz, and the 21-17311-02 which operates at a maximum frequency of 10 MHz; and the 21-17311-00 from a second source, Synertek, also a 7.5 MHz part. All versions are marked "310ES".
External links
- μ/T-11 User's Guide
- T-11 Engineering Specification
- DEC Semiconductor Databook, Volume 1, pp. 361-411
| v • d • e PDP-11 Computers and Peripherals |
|---|
| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
