Difference between revisions of "KDF11-U CPU"

From Computer History Wiki
Jump to: navigation, search
m (bah, typo)
(Note UNIBUS, not QBUS)
Line 1: Line 1:
The '''KDF11-U''' [[PDP-11 architecture|PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/24]] was implemented as a single [[DEC card form factor|hex]] card, the KDF11-UA M7133, using the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]].
+
The '''KDF11-U''' is the [[PDP-11 architecture|PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor|hex]] card, the KDF11-UA M7133, using the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]].
  
 
In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and [[floating point]]), it also included sockets to hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), and two [[asynchronous serial line]]s (led out through the [[backplane]]).
 
In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and [[floating point]]), it also included sockets to hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), and two [[asynchronous serial line]]s (led out through the [[backplane]]).

Revision as of 15:51, 4 February 2018

The KDF11-U is the PDP-11 CPU for the PDP-11/24; it used the UNIBUS, unlike the QBUS of the other KDF11 CPUs. It was implemented as a single hex card, the KDF11-UA M7133, using the same 'Fonz' F-11 chip set as the other KDF11 CPUs.

In addition to the basic CPU functionality (including memory mapping and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two asynchronous serial lines (led out through the backplane).

There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual DIPs were replaced with a pair of custom gate array chips, and the board was re-laid-out.