Difference between revisions of "MS11-L MOS memory"
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It plugs into a [[Modified UNIBUS Device|MUD]] [[backplane]] (only; not [[Small Peripheral Controller|SPC]]). It is a single [[DEC card form factor|hex]] card, the M7891, so it cannot go in the end slots of the backplane. | It plugs into a [[Modified UNIBUS Device|MUD]] [[backplane]] (only; not [[Small Peripheral Controller|SPC]]). It is a single [[DEC card form factor|hex]] card, the M7891, so it cannot go in the end slots of the backplane. | ||
| − | The access time is 385 nsec (typical; 1025 nsec maximum on [[refresh]] conflict), and the cycle time is 510 nsec (1050 nsec maximum on refresh conflict). Refresh time is 570 nsec (typical; 610 nsec maximum); | + | The [[access time]] is 385 nsec (typical; 1025 nsec maximum on [[refresh]] conflict), and the [[cycle time]] is 510 nsec (1050 nsec maximum on refresh conflict). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). |
| − | The board has provision to use battery backup power to retain data during a power outage. | + | The board has provision to use battery backup power to retain data during a power outage. Configuration is by [[Dual Inline Package|DIP]] switches. |
{{PDP-11}} | {{PDP-11}} | ||
[[Category: UNIBUS Memories]] | [[Category: UNIBUS Memories]] | ||
Revision as of 17:13, 16 October 2018
The MS11-L was final UNIBUS main memory from DEC; a single card can hold enough MOS DRAM chips to fill the entire UNIBUS address space. It had a jumper option to enable use on an Extended UNIBUS.
Fully populated with 16Kx1 chips, it is known as the MS11-LD, and holds 256K bytes. The quarter-, half- and three-quarter-populated versions are the MS11-LA, -LB and -LC, respectively; with 64KB, 128KB and 192KB. All versions include on-board parity support.
It plugs into a MUD backplane (only; not SPC). It is a single hex card, the M7891, so it cannot go in the end slots of the backplane.
The access time is 385 nsec (typical; 1025 nsec maximum on refresh conflict), and the cycle time is 510 nsec (1050 nsec maximum on refresh conflict). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum).
The board has provision to use battery backup power to retain data during a power outage. Configuration is by DIP switches.
| v • d • e PDP-11 Computers and Peripherals |
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| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
