KD11-K CPU

The KD11-K was the CPU of the PDP-11/60. It provided the subset PDP-11 memory management, and used the UNIBUS for main memory access (although a built-in cache was standard).

It consisted of a custom 14-slot backplane, and 6 hex boards:

• uWord (M7872)
• Decode (M7873)
• Data Path (M7874)
• KT/Cache (M7875)
• Timing (M7876)
• Status (M7827)

for the basic CPU, held in slots 2-7 of the backplane.

It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, a 4 hex board co-processor which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.

A single slot in the backplane, slot 1, is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store (ROM microcode), or a Diagnostic Control Store.

The remaining slots, 12-14, were SPC slots.

Microcode

It was a microcoded CPU, using 48-bit wide micro-words; the address space of the micro-engine was 2¹² words, divided into 8 blocks. The allocation of the blocks was:

1. Base instructions
2. Console an Error log
3. EIS, Initialization
4. Floating point
5. Floating point
6. ECS
7. ECS/UCS
8. ECS/UCS