Difference between revisions of "PDP-11/45"

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[[Image:PDP11-45.jpg|150px|right|thumb|A PDP11-45]]
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{{Infobox Machine
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| image = PDP11-45.jpg
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| imgwidth = 200px
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| caption = A PDP-11/45
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| name = PDP-11/45
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| manufacturer = [[Digital Equipment Corporation|DEC]]
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| architecture = [[PDP-11 architecture|PDP-11]]
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| form factor = [[minicomputer]]
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| word size = 16 bit
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| virtual address = 16 bit
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| physical address = 18 bit
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| design type = [[microcode]]d
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| bus arch = [[UNIBUS]]/FastBus
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| year introduced = June 1972
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|}}
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The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.
  
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The '''PDP-11/45''' was a fast [[UNIBUS]] [[PDP-11]] system using the KB11-A (early units, prior to 1976) or KB11-D (later) CPU, a high-performance CPU implemented in [[SSI]] [[Schottky TTL]] logic. (The difference between the two was whether they worked with the [[FP11-B]] or [[FP11-C]] [[Floating point processor|FPP]].)
+
The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor|FP11-B]] or [[FP11-C Floating-Point Processor|FP11-C]] [[Floating point processor|FPP]]. The [[FP11 floating point]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).
  
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The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were configured with MOS or bipolar memory, respectively.
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The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor|MOS]] or 300 nsec [[bipolar]] memory, respectively.
  
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Optionally, the machine could be configured with a KT11-C memory management unit; the FP11 floating-point processor was also optional.
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The machine's 18-bit-address UNIBUS allowed it to have up to 256Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].
  
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The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.
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==High-speed memory==
  
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== KB11-A CPU ==
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The MS11 high-speed memory was [[multi-port memory|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was implemented as part of the CPU's [[backplane]]; the other went to a second UNIBUS (the 'B' UNIBUS).
  
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The KB11-A board set included:
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That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access|DMA]] devices on that UNIBUS could do [[input/output|I/O]] to the fast memory, which was accessible only from the CPU when the two UNIBUSes were split.
  
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* M8100 Data and Address Paths
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Note that if the system contained a dual-UNIBUS [[RH11 MASSBUS controller]], devices attached to that could reach the fast memory in a split-UNIBUS system if the RH11's second UNIBUS was attached to the 'B' UNIBUS, giving them a high-speed path to the memory on which there was no contention with the CPU.
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* M8101 General Register and Control
 
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* M8102 Instruction Register and Decode
 
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* M8103 ROM and ROM Control
 
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* M8104 Processor Data and UNIBUS Registers
 
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* M8105 Timing and Miscellaneous Control
 
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* M8106 UNIBUS and Console Control
 
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* M8109 Timing Generator
 
  
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In addition, the CPU includes either:
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The high-speed memory could be configured in two semi-independent banks, each with its own dual-ported M8110 (later M8120) Semiconductor Memory Control module.
  
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* M8116 Segmentation Jumper Board
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When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the 'A' UNIBUS; if that [[address]] was in an MS11, the MS11's controller indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.
  
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used when the KT11-C memory management unit is not present, or:
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A number of products from [[Able Computer]] made use of the FastBus; the [[Able CACHE/45]] (which provided a [[cache]]), and the [[Able SCAT/45]] (which was an MS11 equivalent which could support up to 256 Kbytes of memory).
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* M8107 Segmentation Address Paths
 
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* M8108 Segmentation Status Registers
 
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which comprise the KT11-C.
 
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== KB11-D CPU ==
 
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The KB11-D board set included many of the same boards as the KB11-A, with the following differences:
 
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* The M8102 Instruction Register and Decode was replaced with the M8132
 
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* The M8103 ROM and ROM Control was replaced with the M8123
 
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* The M8106 UNIBUS and Console Control was replaced with the M8119
 
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When the KT11-C memory management unit (termed the KT11-CD in this CPU) was present, the M8108 Segmentation Status Registers board was replaced with the M8108-YA variant.
 
  
 
== hampage.hu ==
 
== hampage.hu ==
 
Quoting:
 
Quoting:
 
<i>
 
<i>
−
Introduced two years after the [[PDP-11/20]], in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.
+
Introduced two years after the [[PDP-11/20]], in June 1972. The KB11 was a faster, [[microcode]]d CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.
  
−
The cycle time of the [[PDP-11/45]] with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.
+
The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.
  
−
The [[PDP-11/50]] was basically the same machine with different memory. The [[PDP-11/55]] ([[KB11D]]) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
+
The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
 
</i>
 
</i>
  
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== Documentation ==
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== Gallery ==
  
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* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual]
 
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== Gallery ==
 
 
[[Image:PDP11-55-geerol.jpg|150px|A PDP-11/55 setup]]
 
[[Image:PDP11-55-geerol.jpg|150px|A PDP-11/55 setup]]
 
[[Image:PDP11-55-geerol2.jpg|150px|Different view of the PDP-11/55 setup]]
 
[[Image:PDP11-55-geerol2.jpg|150px|Different view of the PDP-11/55 setup]]
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[[Image:pdp11-45.jpeg|150px|The "mysterious" PDP-11/45]]
 
[[Image:pdp11-45.jpeg|150px|The "mysterious" PDP-11/45]]
 
[[Image:labor114.jpg|150px|11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.]]
 
[[Image:labor114.jpg|150px|11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.]]
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{{PDP-11}}
 
  
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[[Category:DEC processors]][[Category:UNIBUS processors]]
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==External links==
 +
 
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_SystemMan.pdf PDP-11/45, 11/50 and 11/55 system user's manual] (EK-1145-OP-001)
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1145/DEC-11-HMRMA-A-D_PDP-11_45_Maintenance_Reference_Manual_Nov72.pdf PDP-11/45 maintenance reference manual] (DEC-11-HMRMA-A-D)
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1145/EK-11045-MM-007.pdf PDP-11/45, 11/50 and 11/55 system maintenance manual] (EK-11045-MM-007)
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1145/PDP-11_45_and_70_Maintenance_Course_Handout_Book_1978.pdf PDP-11/45 /70 Maintenance Course handout book]
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun74.pdf PDP-11/45 system engineering drawings (June 1974)]
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf pdp11/45 processor handbook]
 +
 
 +
{{Nav PDP-11}}
 +
 
 +
[[Category: UNIBUS PDP-11s]]

Latest revision as of 22:52, 29 February 2024


PDP-11/45
PDP11-45.jpg
A PDP-11/45
Manufacturer: DEC
Architecture: PDP-11
Year Introduced: June 1972
Form Factor: minicomputer
Word Size: 16 bit
Design Type: microcoded
Physical Address Size: 18 bit
Virtual Address Size: 16 bit
Bus Architecture: UNIBUS/FastBus

The PDP-11/45 was the early fast UNIBUS PDP-11 system, using the KB11-A CPU (early units, prior to 1976) or KB11-D CPU (later units) high-performance CPUs, implemented in SSI Schottky TTL logic.

The difference between the two CPUs was whether they worked with the FP11-B or FP11-C FPP. The FP11 floating point was optional, as was the KT11-C Memory Management Unit (the first implementation of the full PDP-11 Memory Management).

The PDP-11/50 and PDP-11/55 were systems which used the exact same processor, but were sold pre-configured with the special high-speed MS11 Semiconductor Memory System (specific to the PDP-11/45), using 350 nsec MOS or 300 nsec bipolar memory, respectively.

The machine's 18-bit-address UNIBUS allowed it to have up to 256Kbytes of main memory. Later non-DEC products such as the Able ENABLE allowed use of up to 4Mbytes, via an Extended UNIBUS.

High-speed memory

The MS11 high-speed memory was dual-ported: one port went to a special high-speed bus to the CPU (called the Fastbus), which was implemented as part of the CPU's backplane; the other went to a second UNIBUS (the 'B' UNIBUS).

That UNIBUS could either be connected to a second PDP-11 (creating a multi-processor PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that DMA devices on that UNIBUS could do I/O to the fast memory, which was accessible only from the CPU when the two UNIBUSes were split.

Note that if the system contained a dual-UNIBUS RH11 MASSBUS controller, devices attached to that could reach the fast memory in a split-UNIBUS system if the RH11's second UNIBUS was attached to the 'B' UNIBUS, giving them a high-speed path to the memory on which there was no contention with the CPU.

The high-speed memory could be configured in two semi-independent banks, each with its own dual-ported M8110 (later M8120) Semiconductor Memory Control module.

When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the 'A' UNIBUS; if that address was in an MS11, the MS11's controller indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.

A number of products from Able Computer made use of the FastBus; the Able CACHE/45 (which provided a cache), and the Able SCAT/45 (which was an MS11 equivalent which could support up to 256 Kbytes of memory).

hampage.hu

Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.

The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.

The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the PDP-11/70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.

Gallery

A PDP-11/55 setup Different view of the PDP-11/55 setup The frontpanel was even nicer than the /20's. A really wonderful picture of the frontpanel (thanks to Csaba Tóth!) A nice configuration The "mysterious" PDP-11/45 11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.

External links


v • d • e PDP-11 Computers and Peripherals
UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70
PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94

QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93

QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E

Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI

Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management

UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U

Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11

Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11

CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B

Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store

Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P

More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS

PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150   CTI PDP-11s - PRO-325 • PRO-350 • PRO-380

Clones: CM 1420 • SM 1420

Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences

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