Difference between revisions of "LSI-11 CPUs"
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| − | The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]]. | + | The '''LSI-11 CPUs''' were [[Digital Equipment Corporation|DEC]]'s first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]]. |
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| + | The basic [[clock]] μcycle is 350 nsec; simple [[register]]-register [[instruction]]s (e.g. MOV, ADD) took 3.5 μseconds; depending on the exact [[operand]] [[PDP-11 architecture#Operands|modes]] used in a particular instruction, and the [[main memory]] speed (with the [[asynchronous]] QBUS), that could add up to roughly 12 μseconds to that basic time. (The extra time is roughly linear in the number of [[memory cycle]]s, at 1.4-2.1 μseconds per cycle - depending on the operand modes, PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to [[fetch]] the basic instruction.) | ||
They were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, the main [[asynchronous serial line|serial line]] is used as a operating console, using the [[QBUS CPU ODT|ODT functionality]]. | They were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, the main [[asynchronous serial line|serial line]] is used as a operating console, using the [[QBUS CPU ODT|ODT functionality]]. | ||
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==Limitations== | ==Limitations== | ||
| − | Note that ODT will not function correctly in the LSI-11s unless there is [[main memory]] on the [[QBUS]]. The reason for this restriction is unknown: the [[KDF11 CPUs]] and [[KDJ11 CPUs]], which also use ODT, do not have this limitation; e.g. a system consisting only of a [[KDF11-A CPU]] and a serial console will run ODT. | + | Note that ODT will not function correctly in the LSI-11s unless there is [[main memory]] on the [[QBUS]] (at location 0). The reason for this restriction is unknown: the [[KDF11 CPUs]] and [[KDJ11 CPUs]], which also use ODT, do not have this limitation; e.g. a system consisting only of a [[KDF11-A CPU]] and a serial console will run ODT. |
| − | Both LSI-11s are [[QBUS#Variable address size|Q16]] devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 [[backplane]], they will '''only''' function with Q16 [[main memory]]. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11. The reason for the incompatability with Q18 memory is currently unknown.) | + | Both LSI-11s are [[QBUS#Variable address size|Q16]] devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 [[backplane]], they will '''only''' function with Q16 or Q18 [[main memory]]. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11.<!--The reason for the incompatability with Q18 memory is currently unknown.-->) |
==Options== | ==Options== | ||
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They also supported the optional [[KUV11 Writeable Control Store]]. | They also supported the optional [[KUV11 Writeable Control Store]]. | ||
| − | {{PDP- | + | ==See also== |
| + | |||
| + | * [[KDF11 CPUs]] | ||
| + | |||
| + | ==Further reading== | ||
| + | |||
| + | * ''System Differences - LSI-11 vs. LSI-11/23'', [[MicroNote]] #049 | ||
| + | * ''Wake-up Circuit Implementations'', MicroNote #085 | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000323.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978 | ||
| + | |||
| + | {{Nav PDP-11}} | ||
| − | [[Category: PDP-11 | + | [[Category: PDP-11 QBUS Processors]] |
| − | |||
Latest revision as of 16:03, 29 July 2024
The LSI-11 CPUs were DEC's first cost-reduced PDP-11 CPUs, using a microprocessor (the LSI-11 chip set). They also used a new bus, the QBUS.
The basic clock μcycle is 350 nsec; simple register-register instructions (e.g. MOV, ADD) took 3.5 μseconds; depending on the exact operand modes used in a particular instruction, and the main memory speed (with the asynchronous QBUS), that could add up to roughly 12 μseconds to that basic time. (The extra time is roughly linear in the number of memory cycles, at 1.4-2.1 μseconds per cycle - depending on the operand modes, PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to fetch the basic instruction.)
They were the first PDP-11 models to not have a front panel to control them; instead, as a cost-reduction measure, the main serial line is used as a operating console, using the ODT functionality.
The first LSI-11 was a quad board (M7264) with additional functionality on-board. A later board, the LSI-11/2, packaged just the CPU on a dual card.
Limitations
Note that ODT will not function correctly in the LSI-11s unless there is main memory on the QBUS (at location 0). The reason for this restriction is unknown: the KDF11 CPUs and KDJ11 CPUs, which also use ODT, do not have this limitation; e.g. a system consisting only of a KDF11-A CPU and a serial console will run ODT.
Both LSI-11s are Q16 devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 backplane, they will only function with Q16 or Q18 main memory. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11.)
Options
There were CPU options were available for the LSI-11s: the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).
They also supported the optional KUV11 Writeable Control Store.
See also
Further reading
- System Differences - LSI-11 vs. LSI-11/23, MicroNote #049
- Wake-up Circuit Implementations, MicroNote #085
External links
- Mark J. Sebern, A Minicomputer-Compatible Microcomputer System: The DEC LSI-11, in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, Computer Engineering: A DEC View of Hardware Systems Design, Digital Press, Bedford, 1978
| v • d • e PDP-11 Computers and Peripherals |
|---|
| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
