KA11 CPU

The KA11 is the CPU of the PDP-11/20, the first PDP-11.

It was the only PDP-11 CPU which was not micro-programed (since the cheap ROMs which make micro-programming cost-effective in smaller machines were not available at the time it was designed).

Internal structure

The KA11 is basically divided into four main sections:

• Bus Interface
• Data Paths
• Registers
• Control

(There is also a Console section, which allows the machine's console to control the CPU, but it is not involved in 'normal' machine operation.)

The Bus Interface and Control sections communicate with the machine's main bus, the UNIBUS; only the former transfers data, the latter's connection is to allow the KA11 to serve as the 'bus arbitrator' for the UNIBUS. Only the Data Paths section can pass data to the Bus Interface section.

There is a 16x16 register file, of which half are used to hold the machine's general registers; two of the others are used for internal temporary registers (Temp and Source). A number of other internal registers (e.g. the Instruction Register and Bus Address Register) are implemented separately, to make them always available. The Register section communicates only with the Data Path section.

The condition codes are part of the Control section, but are generated in the Data Paths section.

State machine

As noted above, the KA11 does not have microcode; instead, it uses a state machine to control the operation of the CPU. There are 5 major states:

• Fetch - obtain and decode the instruction;
• Source - decode the source field of a double-operand instruction, fetch the data, and store it in a temporary;
• Destination - decode the destination field, and obtain the data;
• Execute - use the data obtained in previous states to perform the requested operation, including writing data back to the destination;
• Service - perform special operations such as interrupts, traps, etc.

Each major state contains a number of minor states, as needed to perform the operations of that state (e.g. perform a bus cycle to fetch a memory word).

Not all instructions pass through all 5 states, although all do pass through 'Fetch'. 'Source' and 'Destination' are not entered if the mode for that operand is 'Register'; only 'full' double-operand instructions (i.e. those with mode bits in the source) will enter 'Source' state.

Data paths

The ALU in the KA11 is an extremely simple one, unlike all other -11's; it can only perform additions.

Each input to the adder has a three-input mux (implemented as a NOR of three inputs with NANDs to enable them), and a latch on the output of the mux (effectively), before the adder. The A mux can select from register data, and complemented register and bus data; the B mux can select register and bus data. The complemented inputs allow the creation of constants (e.g. simultaneously selecting 'register' and 'complemented register' on the A mux creates -1).

A mux on the output allows one-bit shift/rotate operations (the original PDP-11 instruction set does not support multi-bit shifts), as well as byte swapping; the shift capability is used in other ways as well (e.g. in calculating the destinations of branch instructions, which include a word offset).

Implementation

The KA11 was implemented as a set of extended length FLIP CHIPs; most of the circuitry was on quad-height ones, but there were some duals, and a few singles.

They all plugged into a custom backplane, formed from three 4-slot backplane sections wired together into one monolithic unit.

The KA11 board set comprises:

Board	Function
Single
M823	Codes Data
M825	Power Failure and Control
Dual
M224 (two instances)	Data Paths (8 bits; 2 latches, adder)
M225	Registers (16 bits x 16)
M821	Register Control
M822	Flag Control
M824	Priority
Quad
M724	Bus and Console Control
M725	Bus Interface and IR
M726	IR Decode
M727	State Control
M728	Timing and States
M820	Data Path Control