Difference between revisions of "KD11-K CPU"
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| − | The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It | + | The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used the [[UNIBUS]] for [[main memory]] access (although a built-in [[cache]] was standard). |
It consisted of a custom 14-slot [[backplane]], and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]: | It consisted of a custom 14-slot [[backplane]], and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]: | ||
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The remaining slots, 12-14, were [[Small Peripheral Controller|SPC]] slots. | The remaining slots, 12-14, were [[Small Peripheral Controller|SPC]] slots. | ||
| + | |||
| + | ==Microcode== | ||
| + | |||
| + | It was a [[microcode]]d CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2<sup>12</sup> words, divided into 8 blocks. The allocation of the blocks was: | ||
| + | |||
| + | # Base instructions | ||
| + | # Console an Error log | ||
| + | # EIS, Initialization | ||
| + | # Floating point | ||
| + | # Floating point | ||
| + | # ECS | ||
| + | # ECS/UCS | ||
| + | # ECS/UCS | ||
{{PDP-11}} | {{PDP-11}} | ||
Revision as of 03:34, 4 March 2019
The KD11-K was the CPU of the PDP-11/60. It provided the subset PDP-11 memory management, and used the UNIBUS for main memory access (although a built-in cache was standard).
It consisted of a custom 14-slot backplane, and 6 hex boards:
- uWord (M7872)
- Decode (M7873)
- Data Path (M7874)
- KT/Cache (M7875)
- Timing (M7876)
- Status (M7827)
for the basic CPU, held in slots 2-7 of the backplane.
It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, a 4 hex board co-processor which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.
A single slot in the backplane, slot 1, is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store (ROM microcode), or a Diagnostic Control Store.
The remaining slots, 12-14, were SPC slots.
Microcode
It was a microcoded CPU, using 48-bit wide micro-words; the address space of the micro-engine was 212 words, divided into 8 blocks. The allocation of the blocks was:
- Base instructions
- Console an Error log
- EIS, Initialization
- Floating point
- Floating point
- ECS
- ECS/UCS
- ECS/UCS
| v • d • e PDP-11 Computers and Peripherals |
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| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| [Expand] |
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