KB11-B CPU

The KB11-B CPU is the earlier CPU for the PDP-11/70. It is heavily based on the PDP-11/45's KB11-A CPU; the -11/70 is basically an -11/45 with a cache, more main memory, and provision for high/speed I/O device controllers for MASSBUS devices.

Full PDP-11 Memory Management and the cache were standard on all KB11-B's. It used a special 32-bit wide memory bus, the Main Memory Bus, unique to the -11/70, for its bus to main memory; in addition to the speedup of doubling the width, this bus also allowed it to have up to 4 mega-bytes of main memory.

All devices were attached to a separate UNIBUS; DMA devices could gain access to the memory via a UNIBUS map which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to MASSBUS controllers.

The optional FP11-B Floating-Point Processor (full FP11 floating point), and up to four RH70 MASSBUS controllers plugged into the CPU's backplane.

Boards

The basic KB11-B consisted of fifteen hex boards:

• M8130 Data Paths
• M8131 General Registers and ALU Control
• M8132 Instruction Register Decode and Condition Codes
• M8133 ROM and ROM Control
• M8134 Processor Data and UNIBUS Registers
• M8135 Trap and Miscellaneous Control
• M8136 UNIBUS and Console Control
• M8137 System Address Paths
• M8138 System Status Registers
• M8140 System Descriptor amd Console Cables
• M8141 UNIBUS Map
• M8142 Cache Control
• M8143 Cache Address Memory
• M8144 Cache Data Memory
• M8145 Cache Data Paths

and a quad board:

• M8139 Timing Generator

The M8130 through M8139 boards are based on those of the KB11-A CPU of the -11/45; the rest implement the -11/70's extensions (cache - M8142-45, UNIBUS Map - M8141, etc).

See also

• KB11-C CPU

External links

• KB11-B Processor Manual (PDP-11/70) (EK-KB11B-TM-001)
• KB11-B 16-Bit Processor Engineering Drawings (5/1977)