J-11 chip set: Difference between revisions

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New page: 150px|thumb|right|J-11 A cpu for the PDP-11's... this one was a "single chip". {{stub}}
 
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[[Image:J-11 cpu.jpg|150px|thumb|right|J-11]]
[[Image:J-11 cpu.jpg|150px|thumb|right|J-11]]
A cpu for the PDP-11's... this one was a "single chip".
 
The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[CMOS]] implementation of the [[PDP-11]] architecture, implemented in two chips ('Control' and 'Data') carried on a single 60-pin [[DIP]] carrier.
 
It implements the full PDP-11 memory management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11]] floating-point support, it can operate with an [[FPJ11]] floating point accelerator.
 
All uses on DEC PDP-11 CPU boards (all for the [[QBUS]]) contain an external cache.


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[[Category:DEC processors]]
[[Category:QBUS processors]]

Revision as of 12:56, 2 June 2016

J-11

The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.

It implements the full PDP-11 memory management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating-point support, it can operate with an FPJ11 floating point accelerator.

All uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.