KDF11-U CPU: Difference between revisions

From Computer History Wiki
Jump to navigationJump to search
m +cat
Document -YA version of CPU board
Line 2: Line 2:


In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two serial lines (led out through the backplane).
In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two serial lines (led out through the backplane).
There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), to reduce the cost, a number of individual [[DIP]]s were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.


{{PDP-11}}
{{PDP-11}}


[[Category:UNIBUS processors]]
[[Category:UNIBUS processors]]

Revision as of 13:48, 13 January 2017

The KDF11-U PDP-11 CPU for the PDP-11/24 was implemented as a single hex card, the KDF11-UA M7133, using the same 'Fonz' F-11 chip set as the other KDF11 CPUs.

In addition to the basic CPU functionality (including memory mapping and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two serial lines (led out through the backplane).

There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), to reduce the cost, a number of individual DIPs were replaced with a pair of custom gate array chips, and the board was re-laid-out.